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c.
STOP mode
When STOP mode is selected, all internal circuits stop, including the internal
oscillator pin status in STOP mode depends on the settings in the
SYSCR2<DRVE> register. Table 3.4.5, Table 3.4.6 summarizes the state of these
pins in STOP mode.
After STOP mode has been cleared system clock output starts when the
warm-up time has elapsed, in order to allow oscillation to stabilize. See the
sample warm-up times in Table 3.4.4.
Figure 3.4.7 illustrates the timing for clearance of the STOP mode halt state by
an interrupt.
X1
A0 to A23
D0 to D15
RD
WR
Interrupt for
release
Figure 3.4.7 Timing Chart for STOP Mode Halt State Cleared by Interrupt
Table 3.4.4 Sample Warm-up Times after Clearance of STOP Mode
8
01 (2
)
7.1 μ s
Warm-up time
Data
STOP
mode
SYSCR2<WUPTM1:0>
14
10 (2
)
0.455 ms
91C829-23
TMP91C829
Data
= 36 MHz
at f
OSCH
16
11 (2
)
1.820 ms
2006-03-15
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