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Toshiba TLCS-900/L1 Series Manual
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Toshiba TLCS-900/L1 Series Manual

Toshiba TLCS-900/L1 Series Manual

Original cmos 16-bit microcontroller
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TOSHIBA Original CMOS 16-Bit Microcontroller
TLCS-900/L1 Series
TMP91C829
Semiconductor Company

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  • Page 1 TOSHIBA Original CMOS 16-Bit Microcontroller TLCS-900/L1 Series TMP91C829 Semiconductor Company...
  • Page 2 Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, “Points of Note and Restrictions”. Especially, take care below cautions. **CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts = (...

  • Page 3: Outline And Features

    TMP91C829 CMOS 16-Bit Microcontroller TMP91C829FG Outline and Features TMP91C829 is a high-speed 16-bit microcontroller designed for the control of various mid- to large-scale equipment.With 2 Kbytes of boot ROM included, it allows your programs to be erased and rewritten on board. TMP91C829FG comes in a 100-pin flat package. Listed below are the features.
  • Page 4 TMP91C829 (4) External memory expansion • Expandable up to 16 Mbytes (Shared program/data area) • Can simultaneously support 8-/16-bit width external data bus … Dynamic data bus sizing (5) 8-bit timers: 6 channels (6) 16-bit timer/event counter: 1 channel (7) Serial bus interface: 2 channels (8) 10-bit AD converter: 8 channels (9) Watchdog timer (10) Chip select/wait controller: 4 blocks...
  • Page 5 TMP91C829 LVCC 3V (AN3/PA3) ADTRG HVCC 5V CPU (TLCS-900L1) AN0 to AN7 (PA0 to PA7) VREFH 10-bit 8-ch BOOT VREFL AM0/AM1 AVCC converter RESET AVSS EMU0 Clock gear Port A EMU1 32 bits Port 1 (P10 to P17) D8 to D15 Port 2 (P20 to P27) A16 to A23 Port Z...

  • Page 6: Pin Assignment And Pin Functions

    TMP91C829 Pin Assignment and Pin Functions The assignment of input/output pins for the TMP91C829FG, their names and functions are as follows: Pin Assignment Diagram Figure 2.1.1 shows the pin assignment of the TMP91C829FG. Pin name Pin name 63 HVCC (5 V) P27/A23 64 BOOT P26/A22 65...

  • Page 7: Pin Names And Functions

    TMP91C829 Pin Names and Functions The names of the input/output pins and their functions are described below. Table 2.2.1 Pin Names and Functions (1/3) Number Pin Name Functions of Pins D0 to D7 Data (Lower): Bits 0 to 7 of data bus P10 to P17 Port 1: I/O port that allows I/O to be selected at the bit level (when used to the external 8-bit bus)
  • Page 8 TMP91C829 Table 2.2.2 Pin Names and Functions (2/3) Number Pin Name Functions of Pins Port 73: I/O port TA4IN Input Timer A4 input INT3 Input Interrupt request pin 3: Interrupt request pin with programmable level/rising edge/falling edge Port 74: I/O port TA5OUT Output Timer A4 or timer A5 output...
  • Page 9 TMP91C829 Table 2.2.3 Pin Names and Functions (3/3) Number Pin Name Functions of Pins BOOT Input This pin sets boot mode (with pull-up resistor) Input Non-maskable interrupt request pin: Interrupt request pin with programmable falling edge level or with both edge levels programmable AM0 to AM1 Input Address mode : External data bus with select pin...

  • Page 10: Operation

    TMP91C829 Operation This section describes the basic components, functions and operation of the TMP91C829. Notes and restrictions which apply to the various items described here are outlined in section 7. “Points to Note and Restrictions” at the end of this databook. The TMP91C829 incorporates a high-performance 16-bit CPU (The 900/L1 CPU).
  • Page 11 TMP91C829 Read Write Figure 3.1.1 TMP91C829 Reset Timing Example 2006-03-15 91C829-9...

  • Page 12: Outline Of Operation Modes

    TMP91C829 3.1.2 Power On and Power Off of the Supply VCC 5 VCC 3.3 RESET Max 1 [s] Min 10 [ms] Min 0 [s] Max 1 [s] Oscillator operation time + Clock doubler stabilization time Figure 3.1.2 Power Supply On/Off Timing Outline of Operation Modes There are multi chip and multi boot modes.

  • Page 13: Memory Map

    TMP91C829 Memory Map Figure 3.3.1 is a memory map of the TMP91C829. Multi chip mode Multi boot mode 000000H 000000H Internal I/O Internal I/O Direct area (n) (4 Kbytes) (4 Kbytes) 000100H 000100H 001000H 001000H Internal RAM Internal RAM (8 Kbytes) (8 Kbytes) 003000H 003000H...
  • Page 14 TMP91C829 Triple Clock Function and Standby Function The TMP91C829 contains (1) a clock gearing system, (2) a standby controller, and (3) a noise-reducing circuit. It is used for low-power, low-noise systems. The clock operating mode is as follows: (a) Single clock mode (X1, X2 pins only). Figure 3.4.1 shows a transition figure.
  • Page 15 TMP91C829 3.4.1 Block Diagram of System Clock SYSCR0<WUEF> SYSCR2<WUPTM1:0> SYSCR0 φT Warm-up timer (High-frequency oscillator) <PRCK1:0> φT0 fc/16 ÷2 ÷4 ÷2 fc/2 fc/4 fc/8 fc/16 High-frequency ÷2 ÷4 ÷8 ÷16 oscillator SYSCR1<GEAR2,0> OSCH Clock gear TMRA01 to TMRA45 φT0 Prescaler Interrupt TMRB0 controller...
  • Page 16 TMP91C829 3.4.2 SFRs − − − − − SYSCR0 Bit symbol WUEF PRCK1 PRCK0 (00E0H) Read/Write After reset Always Always Always Always Always Warm-up Select prescaler clock Function timer write “1”. write “0”. write “1”. write “0”. write “0”. 00: f Write 0: 01: Reserved Don’t care...
  • Page 17 TMP91C829 − − − − − − EMCCR0 Bit symbol PROTECT EXTIN (00E3H) Read/Write After reset Protect flag Always Always Always Always 1: External Always Always Function 0: OFF write “0”. write “1”. write “0”. write “0”. clock write “1”. write “1”.
  • Page 18 TMP91C829 3.4.3 System Clock Controller The system clock controller generates the system clock signal (f ) for the CPU core and internal I/O. It contains a clock gear circuit for high-frequency (fc) operation. The register SYSCR1<GEAR0:2> sets the high-frequency clock gear to either 1, 2, 4, 8, or 16 (fc, fc/2, fc/4, fc/8, or fc/16).
  • Page 19 TMP91C829 3.4.4 Prescaler Clock Controller For the internal I/O (TMRA01:45, TMRB0 and SIO0, SIO1), there is a prescaler which can divide the clock. The φ T clock input to the prescaler is either the clock f divided by 2 or the clock fc/16 divided by 2.
  • Page 20 TMP91C829 (2) Protection of register contents (Purpose) An item for mistake operation by inputted noise. To execute the program certainty which is occurred mistake operation, the protect-register can be disabled write operation for the specific SFR. Write disabled SFRs 1. CS/WAIT controller B0CS, B1CS, B2CS, B3CS, BEXCS, MSAR0, MSAR1, MSAR2, MSAR3, MAMR0, MAMR1, MAMR2, MAMR3...
  • Page 21 TMP91C829 3.4.6 Standby Controller (1) HALT modes When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1 or STOP mode, depending on the contents of the SYSCR2<HALTM1:0> register. The subsequent actions performed in each mode are as follows: IDLE2: The CPU only is halted.
  • Page 22 TMP91C829 (2) How to clear a HALT mode The halt state can be cleared by a reset or by an interrupt request. The combination of the value in <IFF0:2> of the interrupt mask register and the current HALT mode determine in which ways the HALT mode may be cleared. The details associated with each type of halt state clearance are shown in Table 3.4.3.
  • Page 23 TMP91C829 Table 3.4.3 Source of Halt State Clearance and Halt Clearance Operation Interrupt Enabled Interrupt Disabled Status of Received Interrupt (Interrupt level) ≥ (Interrupt mask) (Interrupt level) < (Interrupt mask) HALT Mode IDLE2 IDLE1 STOP IDLE2 IDLE1 STOP ♦ ♦ ♦...
  • Page 24 TMP91C829 (3) Operation IDLE2 mode In IDLE2 mode only specific internal I/O operations, as designated by the IDLE2 setting register, can take place. Instruction execution by the CPU stops. Figure 3.4.5 illustrates an example of the timing for clearance of the IDLE2 mode halt state by an interrupt.
  • Page 25 TMP91C829 STOP mode When STOP mode is selected, all internal circuits stop, including the internal oscillator pin status in STOP mode depends on the settings in the SYSCR2<DRVE> register. Table 3.4.5, Table 3.4.6 summarizes the state of these pins in STOP mode. After STOP mode has been cleared system clock output starts when the warm-up time has elapsed, in order to allow oscillation to stabilize.
  • Page 26 TMP91C829 Table 3.4.5 Input buffer State Table Input Buffer State In HALT mode (STOP) When the CPU is In HALT mode Input Operating (IDLE2/IDLE1) <DRVE>=1 <DRVE>=0 Port Name Function During When When When When Used When Used When When Name Reset Used as When Used...
  • Page 27 TMP91C829 Table 3.4.6 Output buffer State Table Output Buffer State In HALT mode (STOP) When the CPU is In HALT mode Output Operating (IDLE2/IDLE1) <DRVE>=1 <DRVE>=0 Port Function During When When When When When When When Name When Used Name Reset Used as Used as...
  • Page 28 TMP91C829 3.5 Interrupts Interrupts are controlled by the CPU interrupt mask register SR<IFF2:0> and by the built-in interrupt controller. The TMP91C829 has a total of 35 interrupts divided into the following five types: • Interrupts generated by CPU: 9 sources (Software interrupts, illegal instruction interrupt) •...
  • Page 29 TMP91C829 Interrupt processing Interrupt specified Micro DMA by micro DMA soft start request start vector? Clear interrupt requenst flag Data transfer by micro DMA Interrupt vector value “V” read Interrupt request F/F clear General-purpose Count ← Count − 1 Micro DMA processing interrupt PUSH processing...
  • Page 30 TMP91C829 3.5.1 General-purpose Interrupt Processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. That is also the same as TLCS-900/L and TLCS-900/H. (1) The CPU reads the interrupt vector from the interrupt controller. If the same level interrupts occur simultaneously, the interrupt controller generates an interrupt vector in accordance with the default priority and clears the interrupt request.
  • Page 31 TMP91C829 Table 3.5.1 TMP91C829 Interrupt Vectors and Micro DMA Start Vectors Vector Default Interrupt Source or Source of Micro DMA Micro DMA Type Vector Value Reference Priority Request Start Vector Address − Reset or “SWI0” instruction 0000H FFFF00H − “SWI1” instruction 0004H FFFF04H −...

  • Page 32: Micro Dma Processing

    TMP91C829 3.5.2 Micro DMA Processing In addition to general-purpose interrupt processing, the TMP91C829 supprots a micro DMA function. Interrupt requests set by micro DMA perform micro DMA processing at the highest priority level (Level 6) among maskable interrupts, regardless of the priority level of the particular interrupt source.
  • Page 33 TMP91C829 If a micro DMA request is set for more than one channel at the same time, the priority is not based on the interrupt priority level but on the channel number. The smaller channel number has the higher priority (Channel 0 (High) > Channel 3 (Low)). While the register for setting the transfer source/transfer destination addresses is a 32-bit control register, this register can only effectively output 24-bit addresses.

  • Page 34: Soft Start Function

    TMP91C829 (2) Soft start function In addition to starting the micro DMA function by interrupts, TMP91C829 includes a micro DMA software start function that starts micro DMA on the generation of the write cycle to the DMAR register. Writing 1 to each bit of DMAR register causes micro DMA once (If write 0 to each bitm micro DMA doesn’t operate).
  • Page 35 TMP91C829 (4) Detailed description of the transfer mode register 8 bits DMAM0 to Note: When setting a value in this register, write 0 to the upper 3 Mode DMAM3 bits. Number of Minimum Number of Execution States Execution Time Mode Description Transfer Bytes at fc = 36 MHz Transfer destination address INC mode...
  • Page 36 TMP91C829 3.5.3 Interrupt Controller Operation The block diagram in Figure 3.5.3 shows the interrupt circuits. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit. For each of the 26 interrupt channels there is an interrupt request flag (Consisting of a flip-flop), an interrupt priority setting register and a micro DMA start vector register.
  • Page 37 TMP91C829 Figure 3.5.3 Block Diagram of Interrupt Controller 2006-03-15 91C829-35...
  • Page 38 TMP91C829 (1) Interrupt priority setting registers Symbol Name Address INTAD INT0 INTE0 IADC IADM2 IADM1 IADM0 I0M2 I0M1 I0M0 & INTE0AD INTAD enable INT2 INT1 INT1 & I2M2 I2M1 I2M0 I1M2 I1M1 I1M0 INTE12 INT2 enable INT4 INT3 INT3 I4M2 I4M1 I4M0 I3M2...
  • Page 39 TMP91C829 Symbol Name Address INTTB01 (TMRB0) INTTB00 (TMRB0) Interrupt ITB01C ITB01M2 ITB01M1 ITB01M0 ITB00C ITB00M2 ITB00M1 ITB00M0 INTETB0 enable TMRB0 (Reserved) INTTBOF0 (overflow) Interrupt enable ITF0C ITF0M2 ITF0M1 ITF0M0 INTETB0V TMRB0V (overflow) INTTX0 INTRX0 Interrupt ITX0C ITX0M2 ITX0M1 ITX0M0 IRX0C IRX0M2 IRX0M1 IRX0M0...

  • Page 40: External Interrupt Control

    TMP91C829 (2) External interrupt control Symbol Name Address − I2EDGE I2LE I1DGE I1LE I0EDGE I0LE NMIREE Interrupt Write “0”. INT2EDGE INT2EDGE INT1EDGE INT1EDGE INT0EDGE INT0 1: Operates IIMC0 input mode (Prohibit 0: Rising 0: Edge 0: Rising 0: Edge 0: Rising 0: Edge even on control 0...
  • Page 41 TMP91C829 Setting functions on external interrupt pins Interrupt Pin Mode Setting Method <NMIREE> = 0 Falling edge <NMIREE> = 1 Both falling and rising edges <I0LE> = 0, <I0EDGE> = 0 Rising edge <I0LE> = 0, <I0EDGE> = 1 Falling edge INT0 <I0LE>...
  • Page 42 TMP91C829 (4) Micro DMA start vector registers These registers assign micro DMA processing to sets which source corresponds to DMA. The interrupt source whose micro DMA start vector value matches the vector set in one of these registers is designated as the micro DMA start source. When the micro DMA transfer counter value reaches zero, the micro DMA transfer end interrupt corresponding to the channel is sent to the interrupt controller, the micro DMA start vector register is cleared, and the micro DMA start source for the...
  • Page 43 TMP91C829 (6) Notes The instruction execution unit and the bus interface unit in this CPU operate independently. Therefore if, immediately before an interrupt is generated, the CPU fetches an instruction which clears the corresponding interrupt request flag (Note), the CPU may execute this instruction in between accepting the interrupt and reading the interrupt vector.

  • Page 44: Port Functions

    TMP91C829 Port Functions The TMP91C829 features 53 bit settings which relate to the various I/O ports. As well as general-purpose I/O port functionality, the port pins also have I/O functions which relate to the built-in CPU and internal I/Os. Table 3.6.1 lists the functions of each port pin. Table 3.6.2 lists the I/O registers and their specifications.
  • Page 45 TMP91C829 Table 3.6.2 I/O Registers and Their Specifications (1/2) I/O Registers Port Name Specification PnCR PnFC Port 1 P10 to P17 Input port Output port D8 to D15 bus Port 2 P20 to P27 Output port A16 to A23 output Port Z Input port (without PU) Input port (with PU)
  • Page 46 TMP91C829 Table 3.6.3 I/O Registers and Their Specifications (2/2) I/O Registers Port Name Specification PnCR PnFC Port 8 Input port (without PU) Input port (with PU) Output port TXD0 output Input port/RXD0 input (without PU) None Input port/RXD0 input (with PU) Output port Input port/SCLK0/CTS0 input (without PU) Input port/SCLK0/CTS0 input (with PU)
  • Page 47 TMP91C829 After a reset the port pins listed below function as general-purpose I/O port pins. A reset sets I/O pins which can be programmed for either input or output to be input port pins. Setting the port pins for internal function use must be done in software. Note about bus release and programmable pull-up I/O port pins = 0), the output buffers for D0 to D15, A0 to A23, When the bus is released (e.g., when...
  • Page 48 TMP91C829 Figure 3.6.1 shows an example external interface circuit when the bus release function is used. When the bus is released, neither the internal memory nor the internal I/O can be accessed. However, the internal I/O continues to operate. As a result, the watchdog timer also continues to run.
  • Page 49 TMP91C829 3.6.1 Port 1 (P10 to P17) Port 1 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P1CR. Resetting, the control register P1CR to 0 and sets port 1 to input mode. In addition to functioning as a general-purpose I/O port, port 1 can also function as an address data bus (D8 to D15).
  • Page 50 TMP91C829 3.6.2 Port 2 (P20 to P27) Port 2 is an 8-bit output port. In addition to functioning as a output port, port 2 can also function as an address bus (A16 to A23). Each bit can be set individually for address bus using the function register P2FC. Resetting sets all bits of the function register P2FC to 1 and sets port 2 to address bus.
  • Page 51 TMP91C829 3.6.3 Port 5 (P53 to P56) Port 5 is an 4-bit general-purpose I/O port. I/O is set using control register P5CR and P5FC. Resetting resets all bits of the output latch P5 to 1, the control register P5CR and the function register P5FC to 0 and sets P52 to P56 to input mode with pull-up register.
  • Page 52 TMP91C829 Reset Direction control (on bit basis) P5CR write Function control (on bit basis) P5FC write P-ch (Programmable pull up) Output P54( BUSAK latch Output buffer P5 write BUSAK P5 read Figure 3.6.7 Port 54 Reset Direction control (on bit basis) P-ch (Programmable pull up) P5CR write Output...
  • Page 53 TMP91C829 Reset Direction control (on bit basis) P5CR write Function control (on bit basis) P5FC write P-ch (Programmable pull up) Output latch P56 (INT0) P5 write Output buffer selector P5 write Level or edge INT0 Rising edge or falling edge IIMC0<I0LE, I0EDGE>...
  • Page 54 TMP91C829 Port 5 Register Bit symbol (000DH) Read/Write After reset Data from external port (Output latch register is set to 1.) Function 0(Output latch register): Pull-up resistor OFF 1(Output latch register): Pull-up resistor ON Port 5 Control Register P5CR Bit symbol P56C P55C P54C...
  • Page 55 TMP91C829 3.6.4 Port 6 (P60 to P63) Port 6 is a 4-bit output port. When reset, the P62 latch is cleared to 0 while the P60 to P63 output latches are set to 1. In addition to functioning as an output port, this port can output standard chip select signals ( ).
  • Page 56 TMP91C829 Port 6 Register Bit symbol (0012H) Read/Write After reset Port 6 Function Register P6FC Bit symbol P63F P62F P61F P60F (0015H) Read/Write After reset 0: Port 1 1: Function Note: Read-modify-write is prohibited for the registers P6FC. Port (P60) Port (P61) Port (P62) Port (P63)
  • Page 57 TMP91C829 3.6.5 Port 7 (P70 to P75) Port 7 is a 6-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets port 7 to be an input port. In addition to functioning as a general-purpose I/O port, the individual port can also have the following functions: Port 70 and 73 can function as the inputs TA0IN and TA4IN to the 8-bit timer, and port 71, 72 and 74 can function as the 8-bit timer outputs TA1OUT, TA3OUT and TA5OUT.
  • Page 58 TMP91C829 Reset Direction control (on bit basis) P7CR write Function control (on bit basis) P7FC write Output latch P71 (TA1OUT) Selector P74 (TA5OUT) P7 write Timer F/F OUT TA1OUT: TMRA1 TA5OUT: TMRA5 Selector P7 read Figure 3.6.15 Port 71, 74 Reset Direction control (on bit basis)
  • Page 59 TMP91C829 Port 7 Register Bit symbol (0013H) Read/Write After reset Data from external port (Output latch register is set to 1.) Port 7 Control Register P7CR Bit symbol P75C P74C P73C P72C P71C P70C (0016H) Read/Write After reset Function 0: Input 1: Output Port 7 I/O setting Input Output...
  • Page 60 TMP91C829 3.6.6 Port 8 (P80 to P87) Port 80 to 87 constitute a 8-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets P80 to P87 to be an input port. It also sets all bits of the output latch register to 1. In addition to functioning as general-purpose I/O port, P80 to P87 can also function as the I/O for serial channels 0.
  • Page 61 TMP91C829 (2) Port 81 (RXD0), 85 (RXD1) Port 81, 85 are I/O port and can also be used as RXD input pin for the serial channels. Reset P-ch (Programmable pull up) Derection control (on bit basis) P8CR write P81 (RXD0) Output latch P85 (RXD1) Output buffer...
  • Page 62 TMP91C829 (4) Port 83 ( ), 87 ( Port 83, 87 are I/O port and can also be used as output for the received data request signal. Reset Direction control (on bit basis) P8CR write Function control (on bit basis) P8FC write P-ch (Programmable pull up) P83 (...
  • Page 63 TMP91C829 Port 8 Register Bit symbol (0018H) Read/Write After reset Data from external port (Output latch register is set to 1.) Function 0(Output latch register) : Pull-up resistor OFF 1(Output latch register): Pull-up resistor ON Port 8 Control Register P8CR Bit symbol P87C P86C...
  • Page 64 TMP91C829 3.6.7 Port 9 (P90, P93 to P96) Port 9 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or output, Resetting sets port 9 to be an input port, it also sets all bits in the output latch register P9 to 1.
  • Page 65 TMP91C829 (2) P93 to P96 Reset Direction control (on bit basis) P9CR write P93 (TB0IN0) Output latch P94 (TB0IN1) P9 write Selector P9 read TB0IN0 TB0IN1 Reset Direction control (on bit basis) P9CR write Function control (on bit basis) P9FC write Output latch P9 write Selector...
  • Page 66 TMP91C829 Port 9 Register Bit symbol (0019H) Read/Write Data from After reset Data from external port external port (Output latch register is set to 1.) (Output latch register is set to 1.) Port 9 Control Register P9CR Bit symbol P96C P95C P94C P93C...
  • Page 67 TMP91C829 3.6.8 Port A (PA0 to PA7) Port A is an 8-bit input port and can also be used as the analog input pins for the internal AD converter. PA0 to PA7 , AN0 ADTRG Port A read to AN7) Conversion Channel result...
  • Page 68 TMP91C829 3.6.9 Port Z (PZ2, PZ3) Port Z is a 4-bit general-purpose I/O port. I/O is set using control register PZCR and PZFC. Resetting resets all bits of the output latch PZ to 1, the control register PZCR and the function register PZFC to 0 and sets PZ2 and PZ3 to input mode with pull-up register. In addition to functioning as a general-purpose I/O port.
  • Page 69 TMP91C829 Port Z Register Bit symbol (007DH) Read/Write After reset Data from external port (Output latch register is set to 1.) Port Z Control Register PZCR Bit symbol (007EH) Read/Write After reset Function 0: Input 1: Output Setting port Z as I/O Input Output Port Z Control Register...

  • Page 70: Chip Select/Wait Controller

    TMP91C829 Chip Select/Wait Controller On the TMP91C829, four user specifiable address areas (CS0 to CS3) can be set. The data bus width and the number of waits can be set independently for each address area (CS0 to CS3 plus any other). The pins (which can also function as P60 to P63) are the respective output pins for the areas CS0 to CS3.
  • Page 71 TMP91C829 (1) Memory start address registers Figure 3.7.1 shows the memory start address registers. The memory start address registers MSAR0 to MSAR3 determine the start addresses for the memory areas CS0 to CS3 respectively. The eight most significant bits (A23 to A16) of the start address should be set in <S23:16>.
  • Page 72 TMP91C829 (2) Memory address mask registers Figure 3.7.3 shows the memory address mask registers. The size of each of the areas CS0 to CS3 can be set by specifying a mask in the corresponding memory address mask register (MAMR0 to MAMR3). Each bit in a memory address mask register (MAMR0 to MAMR3) which is set to 1 masks the corresponding bit of the start address which has been set in the corresponding memory start address register (MSAR0 to MSAR3).
  • Page 73 TMP91C829 (3) Setting memory start addresses and address areas Figure 3.7.4 shows an example in which CS0 is specified to be a 64-Kbyte address area starting at 010000H. First, MSAR0<S23:16>, the eight most significant bits of the start address register and which correspond to the memory start address, are set to 01H.
  • Page 74 TMP91C829 (4) Address area size specification Table 3.7.1 shows the valid area sizes for each CS area and indicates which method can be used to make the size setting. A “Δ” indicates that it is not possible to set the area size in question using the memory start address register and memory address mask register.
  • Page 75 TMP91C829 3.7.2 Chip Select/Wait Control Registers Figure 3.7.5 lists the chip select/wait control registers. The master enable/disable, chip select output waveform, data bus width, and number of wait states for each address area (CS0 to CS3 plus any other) are set in the respective chip select/wait control registers, B0CS to B3CS or BEXCS.
  • Page 76 TMP91C829 (1) Master enable bits Bit7 (<B0E>, <B1E>, <B2E>, or <B3E>) of a chip select/wait control register is the master bit which is used to enable or disable settings for the corresponding address area. Writing 1 to this bit enables the settings. A reset disables <B0E>, <B1E> and <B3E>...
  • Page 77 TMP91C829 (3) Wait control Bits 0 to 2 (<B0W0:2>, <B1W0:2>, <B2W0:2>, <B3W0:2>, or <BEXW0:2>) of a chip select/wait control register specify the number of waits that are to be inserted when the corresponding memory area is accessed. The following types of wait operation can be specified using these bits. Bit settings other than those listed in the table should not be made.
  • Page 78 TMP91C829 (6) Procedure for setting chip select/wait control When using the chip select/wait control function, set the registers in the following order: Set the memory start address registers MSAR0 to MSAR3. Set the start addresses for CS0 to CS3. Set the memory address mask registers MAMR0 to MAMR3. Set the sizes of CS0 to CS3.
  • Page 79 TMP91C829 3.7.3 Connecting External Memory Figure 3.7.6 shows an example of how to connect external memory to the TMP91C829. In this example the ROM is connected using a 16-bit bus. The RAM and I/O are connected using an 8-bit bus. TMP91C829 Address bus Upper byte...

  • Page 80: 8-Bit Timers (Tmra)

    TMP91C829 8-Bit Timers (TMRA) The TMP91C829 features six built-in 8-bit timers. These timers are paired into three modules: TMRA01, TMRA23 and TMRA45. Each module consists of two channels and can operate in any of the following four operating modes. • 8-bit interval timer mode •...
  • Page 81 TMP91C829 3.8.1 Block Diagrams Figure 3.8.1 TMRA01 Block Diagram 2006-03-15 91C829-79...
  • Page 82 TMP91C829 Figure 3.8.2 TMRA23 Block Diagram 2006-03-15 91C829-80...
  • Page 83 TMP91C829 Figure 3.8.3 TMRA45 Block Diagram 2006-03-15 91C829-81...
  • Page 84 TMP91C829 3.8.2 Operation of Each Circuit (1) Prescalers A 9-bit prescaler generates the input clock to TMRA01. The clock φT0 is divided by 4 and input to this prescaler. φT0 can be either f fc/16 and is selected using the prescaler clock selection register SYSCR0<PRCK1:0>. The prescaler’s operation can be controlled using TA01RUN<TA0PRUN>...
  • Page 85 TMP91C829 (3) Timer registers (TA0REG and TA1REG) These are 8-bit registers which can be used to set a time interval. When the value set in the timer register TA0REG or TA1REG matches the value in the corresponding up counter, the comparator match detect signal goes active. If the value set in the timer register is 00H, the signal goes active when the up counter overflows.
  • Page 86 TMP91C829 (4) Comparator (CP0) The comparator compares the value in an up counter with the value set in a timer register. If they match, the up counter is cleared to zero and an interrupt signal (INTTA0 or INTTA1) is generated. If timer flip-flop inversion is enabled, the timer flip-flop is inverted at the same time.
  • Page 87 TMP91C829 3.8.3 SFRs TMRA01 Run Register TA01RUN Bit symbol TA0RDE I2TA01 TA01PRUN TA1RUN TA0RUN (0100H) Read/Write After reset Function Double IDLE2 8-bit timer run/stop control buffer 0: Stop 0: Stop and clear 0: Disable 1: Operate 1: Run (Count up) 1: Enable TA0REG double buffer control Timer run/stop control...
  • Page 88 TMP91C829 TMRA45 Run Register TA45RUN Bit symbol TA4RDE I2TA45 TA45PRUN TA5RUN TA4RUN (0110H) Read/Write After reset Function Double IDLE2 8-bit timer run/stop control buffer 0: Stop 0: Stop and clear 0: Disable 1: Operate 1: Run (Count up) 1: Enable TA4REG double buffer control Timer run/stop control Disable...
  • Page 89 TMP91C829 TMRA01 Mode Register TA01MOD Bit symbol TA01M1 TA01M0 PWM01 PWM00 TA1CLK1 TA1CLK0 TA0CLK1 TA0CLK0 (0104H) Read/Write After reset Function Operation mode PWM cycle Source clock for TMRA1 Source clock for TMRA0 00: 8-bit timer mode 00: Reserved 00: TA0TRG 00: TA0IN pin 01: φT1 01: φT1...
  • Page 90 TMP91C829 TMRA23 Mode Register TA23MOD Bit symbol TA23M1 TA23M0 PWM21 PWM20 TA3CLK1 TA3CLK0 TA2CLK1 TA2CLK0 (010CH) Read/Write After reset Function Operation mode PWM cycle TMRA3 clock for TMRA3 TMRA2 clock for TMRA2 00: 8-bit timer mode 00: Reserved 00: TA2TRG 00: Reserved 01: φT1 01: φT1...
  • Page 91 TMP91C829 TMRA45 Mode Register TA45MOD Bit symbol TA45M1 TA45M0 PWM41 PWM40 TA5CLK1 TA5CLK0 TA4CLK1 TA4CLK0 (0114H) Read/Write After reset Function Operation mode PWM cycle Source clock for TMRA5 Source clock for TMRA4 00: 8-bit timer mode 00: Reserved 00: TA4TRG 00: TA4IN pin 01: φT1 01: φT1...
  • Page 92 TMP91C829 TMRA1 Flip-flop Control Register TA1FFCR Bit symbol TA1FFC1 TA1FFC0 TA1FFIE TA1FFIS (0105H) Read/Write After reset Read- Function 00: Invert TA1FF TA1FF TA1FF modify-write 01: Set TA1FF control for inversion instructions 10: Clear TA1FF inversion select 11: Don’t care 0: Disable 0: TMRA0 prohibited.
  • Page 93 TMP91C829 TMRA3 Flip-flop Control Register TA3FFCR Bit symbol TA3FFC1 TA3FFC0 TA3FFIE TA3FFIS (010DH) Read/Write After reset Read- Function 00: Invert TA3FF TA3FF TA3FF modify-write 01: Set TA3FF control for inversion instructions 10: Clear TA3FF inversion select 11: Don’t care 0: Disable 0: TMRA2 prohibited.
  • Page 94 TMP91C829 TMRA5 Flip-flop Control Register TA5FFCR Bit symbol TA5FFC1 TA5FFC0 TA5FFIE TA5FFIS (0115H) Read/Write After reset Read- Function 00: Invert TA5FF TA5FF TA5FF modify-write 01: Set TA5FF control for inversion instructions 10: Clear TA5FF inversion select 11: Don’t care 0: Disable 0: TMRA4 prohibited.
  • Page 95 TMP91C829 TMRA register − TA0REG bit Symbol (0102H) Read/Write After reset Undefined − TA1REG bit Symbol (0103H) Read/Write After reset Undefined − TA2REG bit Symbol (010AH) Read/Write After reset Undefined − TA3REG bit Symbol (010BH) Read/Write After reset Undefined − TA4REG bit Symbol (0112H)
  • Page 96 TMP91C829 3.8.4 Operation in Each Mode (1) 8-bit timer mode Both TMRA0 and TMRA1 can be used independently as 8-bit interval timers. Generating interrupts at a fixed interval (Using TMRA1) To generate interrupts at constant intervals using TMRA1 (INTTA1), first stop TMRA1 then set the operation mode, input clock and a cycle to TA01MOD and TA1REG register, respectively.
  • Page 97 TMP91C829 Generating a 50% duty ratio square wave pulse The state of the timer flip-flop (TA1FF) is inverted at constant intervals and its status output via the timer output pin (TA1OUT). Example: To output a 1.32 μs square wave pulse from the TA1OUT pin at fc = 36 MHz, use the following procedure to make the appropriate register settings.
  • Page 98 TMP91C829 Making TMRA1 count up on the match signal from the TMRA0 comparator Select 8-bit timer mode and set the comparator output from TMRA0 to be the input clock to TMRA1. Comparator output (TMRA0 match) TMRA0 up counter (when TA0REG = 5) TMRA1 up counter (when TA1REG = 2) TMRA1 match output...
  • Page 99 TMP91C829 The comparator match signal is output from TMRA0 each time the up counter UC0 matches TA0REG, where the up counter UC0 is not be cleared. In the case of the TMRA1 comparator, the match detect signal is output on each comparator pulse on which the values in the up counter UC1 and TA1REG match.
  • Page 100 TMP91C829 In this mode a programmable square wave is generated by inverting the timer output each time the 8-bit up counter (UC0) matches the value in one of the timer registers TA0REG or TA1REG. The value set in TA0REG must be smaller than the value set in TA1REG. Although the up counter for TMRA1 (UC1) is not used in this mode, TA01RUN<TA1RUN>...
  • Page 101 TMP91C829 Example: To generate 1/4 duty 50kHz pulses (at fc = 36 MHz): 20 μs * Clock state System clock: High frequency (fc) Clock gear: 1 (fc) Prescaler clock: f Calculate the value which should be set in the timer register. To obtain a frequency of 50kHz, the pulse cycle t should be: t = 1/50 kHz = 20 μs φT1 = (2...
  • Page 102 TMP91C829 (4) 8-bit PWM output mode This mode is only valid for TMRA0. In this mode, a PWM pulse with the maximum resolution of 8 bits can be output. When TMRA0 is used the PWM pulse is output on the TA1OUT pin (which is also used as P71).
  • Page 103 TMP91C829 In this mode the value of the register buffer will be shifted into TA0REG if 2 overflow is detected when the TA0REG double buffer is enabled. Use of the double buffer facilitates the handling of low duty ratio waves. Match with TA0REG Up counter = Q Up counter = Q...
  • Page 104 TMP91C829 Table 3.8.3 PWM Cycle at fc = 36 MHz PWM Cycle Select Prescaler Gear Value Clock <GEAR2:0> <PRCK1:0> φT1 φT4 φT16 φT1 φT4 φT16 φT1 φT4 φT16 14.2 μs 56.8 μs 227 μs 28.4 μs 455 μs 56.8 μs 227 μs 910 μs 000 (fc)
  • Page 105 TMP91C829 16-Bit Timer/Event Counters (TMRB) The TMP91C829 incorporates multifunctional 16-bit timer/event counter (TMRB0) which has the following operation modes: • 16-bit interval timer mode • 16-bit event counter mode • 16-bit programmable pulse generation (PPG) mode The timer/event counter channel consists of a 16-bit up counter, two 16-bit timer registers (One of them with a double-buffer structure), two 16-bit capture registers, two comparators, a capture input controller, a timer flip-flop and a control circuit.
  • Page 106 TMP91C829 3.9.1 Block Diagrams Figure 3.9.1 Block Diagram of TMRB0 2006-03-15 91C829-104...
  • Page 107 TMP91C829 3.9.2 Operation of Each Block (1) Prescaler The 5-bit prescaler generates the source clock for TMRB0. The prescaler clock (φT0) is divided clock (divided by 4) from selected clock by the register SYSCR0<PRCK1:0> of clock gear. This prescaler can be started or stopped using TB0RUN<TB0RUN>. Counting starts when <TB0RUN>...
  • Page 108 TMP91C829 (3) Timer registers (TB0RG0H/L and TB0RG1H/L) These two 16-bit registers are used to set the interval time. When the value in the up counter UC0 matches the value set in this timer register, the comparator match detect signal will go active. Setting data for both upper and lower registers is always needed.
  • Page 109 TMP91C829 (5) Capture input control This circuit controls the timing to latch the value of up counter UC0 into TB0CP0, TB0CP1. latch timing capture register determined TB0MOD<TB0CPM1:0>. In addition, the value in the up counter can be loaded into a capture register by software.
  • Page 110 TMP91C829 3.9.3 SFRs TMRB0 Run Register − TB0RUN Bit symbol TB0RDE I2TB0 TB0PRUN TB0RUN (0180H) Read/Write After reset Function Double Always write IDLE2 16-bit timer run/stop control buffer “0”. 0: Stop 0: Stop and clear 0: Disable 1: Operate 1: Run (Count up) 1: Enable Count operation Stop and clear...
  • Page 111 TMP91C829 TMRB0 Run Register TB0MOD Bit symbol TB0CT1 TB0ET1 TB0CP0I TB0CPM1 TB0CPM0 TB0CLE TB0CLK1 TB0CLK0 (0182H) Read/Write After reset Function TB0FF1 inversion Execute Capture timing Control up TMRB0 source clock Read 0: Disable trigger software 00: Disable counter 00: TB0IN0 pin -modify 01: TB0IN0 ↑...
  • Page 112 TMP91C829 TMRB0 Flip-flop Control Register TB0FFCR Bit symbol TB0FF1C1 TB0FF1C0 TB0C1T1 TB0C0T1 TB0E1T1 TB0E0T1 TB0FF0C1 TB0FF0C0 (0183H) Read/Write After reset Function Control TB0FF1 TB0FF0 inversion trigger Control TB0FF0 Read 00: Invert 0: Disable trigger 00: Invert -modify 01: Set 1: Enable trigger 01: Set -write 10: Clear...
  • Page 113 TMP91C829 TMRB0 Register – TB0RG0L bit Symbol (0188H) Read/Write After reset Undefined – TB0RG0H bit Symbol (0189H) Read/Write After reset Undefined – TB0RG1L bit Symbol (018AH) Read/Write After reset Undefined – TB0RG1H bit Symbol (018BH) Read/Write After reset Undefined Note: The above registers are prohibited read-modify-write instruction. Figure 3.9.5 TMRB Registers 2006-03-15 91C829-111...
  • Page 114 TMP91C829 3.9.4 Operation in Each Mode (1) 16-bit interval timer mode Generating interrupts at fixed intervals In this example, the interrupt INTTB01 is set to be generated at fixed intervals. The interval time is set in the timer register TB0RG1. ←...
  • Page 115 TMP91C829 (3) 16-bit programmable pulse generation (PPG) output mode Square wave pulses can be generated at any frequency and duty ratio. The output pulse may be either low-active or high-active. The PPG mode is obtained by inversion of the timer flip-flop TB0FF0 that is to be enabled by the match of the up counter UC0 with timer register TB0RG0 or TB0RG1 and to be output to TB0OUT0.
  • Page 116 TMP91C829 The following block diagram illustrates this mode. TB0RUN<TB0RUN> TB0OUT0 (PPG output) Selector TB0IN0 φT1 16-bit up counter Clear φT4 (TB0FF0) φT16 Match 16-bit comparator 16-bit comparator Selector TB0RG0 TB0RG0-WR Register buffer 0 TB0RG1 TB0RUN<TB0RDE> Internal data bus Figure 3.9.7 Block Diagram of 16-Bit Mode The following example shows how to set 16-bit PPG output mode: ←...
  • Page 117 TMP91C829 3.10 Serial Channel TMP91C829 includes one serial I/O channel. Either UART mode (Asynchronous transmission) or I/O interface mode (Synchronous transmission) can be selected. • I/O interface mode Mode 0: For transmitting and receiving I/O data using the synchronizing signal SCLK for extending I/O. Mode 1: 7-bit data •...
  • Page 118 TMP91C829 STS0 and STS1 pins are built in port P83 and P87. STS0 and STS1 are the request signal for the next data send to the CPU. P8CR sets port as output mode, P8FC sets STS using mode, and bit 0 of SC0MOD1 (SC1MOD1) register sets low level. Then STS is enable to start to transfer the data.

  • Page 119: Block Diagrams

    TMP91C829 3.10.1 Block Diagrams Figure 3.10.2 is a block diagram representing serial channel 0. Prescaler φT0 16 32 64 φT2 φT8 φT32 Serial clock generation circuit BR0CR TA0TRG <BR0CK1:0> (from TMRA0) BR0CR BR0ADD <BR0S3:0> <BR0K3:0> φT0 UART mode φT2 SIOCLK φT8 φT32 BR0CR...
  • Page 120 TMP91C829 Prescaler φT0 16 32 64 φT2 φT8 φT32 Serial clock generation circuit BR1CR TA0TRG <BR0CK1:0> (from TMRA0) BR1CR BR1ADD <BR1S3:0> <BR1K3:0> φT0 UART mode φT2 SIOCLK φT8 φT32 BR1CR <BR1ADDE> SC1MOD0 SC1MOD0 Baud rate <SC1:0> <SM1:0> generator ÷2 SCLK1 interface mode Shared with P86...
  • Page 121 TMP91C829 3.10.2 Operation of Each Circuit (1) Prescaler, prescaler clock select There is a 6-bit prescaler for waking serial clock. The clock selected using SYSCR<PRCK1:0> is divided by 4 and input to the prescaler as φT0. The prescaler can be run by selecting the baud rate generator as the waking serial clock. Table 3.10.2 shows prescaler clock resolution into the baud rate generator.
  • Page 122 TMP91C829 (2) Baud rate generator The baud rate generator is a circuit which generates transmission and receiving clocks which determine the transfer rate of the serial channels. The input clock to the baud rate generator, φT0, φT2, φT8 or φT32, is generated by the 6-bit prescaler which is shared by the timers.
  • Page 123 TMP91C829 • N + (16 − K)/16 divider (Only UART mode) Accordingly, when the source clock frequency (fc) = 4.8 MHz, the input clock frequency = φT0, the frequency divider N (BR0CR<BR0S3:0>) = 7, K (BR0ADD<BR0K3:0>) = 3, and BR0CR<BR0ADDE> = 1, the baud rate in UART mode is as follows: * Clock state System clock:...
  • Page 124 TMP91C829 Table 3.10.3 Transfer Rate Selection (when baud rate generator is used and BR0CR<BR0ADDE> = 0) Unit (kbps) Input Clock φT0 φT2 φT8 φT32 fc [MHz] Frequency Divider N (BR0CR<BR0S3:0>) 9.830400 76.800 19.200 4.800 1.200 ↑ 38.400 9.600 2.400 0.600 ↑...
  • Page 125 TMP91C829 (3) Serial clock generation circuit This circuit generates the basic clock for transmitting and receiving data. • In I/O interface mode In SCLK output mode with the setting SC0CR<IOC> = 0, the basic clock is generated by dividing the output of the baud rate generator by 2, as described previously.
  • Page 126 TMP91C829 (6) The receiving buffers To prevent overrun errors, the receiving buffers are arranged in a double-buffer structure. Received data is stored one bit at a time in receiving buffer 1 (which is a shift register). When 7 or 8 bits of data have been stored in receiving buffer 1, the stored data is transferred to receiving buffer 2 (SC0BUF);...

  • Page 127: Handshake Function

    TMP91C829 Handshake function Use of pin allows data can be sent in units of one frame; thus, overrun CTS0 errors can be avoided. The handshake functions is enabled or disabled by the SC0MOD<CTSE> setting. When the pin goes high on completion of the current data send, data CTS0 transmission is halted until the pin goes low again.
  • Page 128 TMP91C829 (9) Transmission buffer The transmission buffer (SC0BUF) shifts out and sends the transmission data written from the CPU, in order one bit at a time starting with the least significant bit (LSB) and finishing with the most significant bit (MSB). When all the bits have been shifted out, the empty transmission buffer generates an INTTX0 interrupt.
  • Page 129 TMP91C829 (12) Timing generation In UART mode Receiving 8 Bits + Parity Mode 9 Bits 8 Bits, 7 Bits + Parity, 7 Bits (Note) (Note) Interrupt timing Center of last bit Center of last bit Center of stop bit (Bit8) (Parity bit) Framing error timing Center of stop bit...
  • Page 130 TMP91C829 3.10.3 SFRs SC0MOD0 Bit symbol CTSE (0202H) Read/Write After reset Function Transfer Hand shake Receive Wakeup Serial transmission mode Serial transmission clock data bit8 0: CTS function function 00: I/O interface Mode (UART) disable 0: Receive 0: Disable 01: 7-bit UART mode 00: TMRA0 trigger 1: CTS disable...
  • Page 131 TMP91C829 SC1MOD0 Bit symbol CTSE (020AH) Read/Write After reset Function Transfer Hand shake Receive Wakeup Serial transmission mode Serial transmission clock data bit8 0: CTS function function 00: I/O interface mode (UART) disable 0: Receive 0: Disable 01: 7-bit UART mode 00: TMRA0 trigger 1: CTS disable...
  • Page 132 TMP91C829 SC0CR EVEN OERR PERR FERR SCLKS Bit symbol (0201H) R (Cleared to 0 when read.) Read/Write After reset Undefined Received Parity Parity 0: Baud rate Function 0: SCLK0 data bit8 0: Odd addition generator 1: Error 1: Even 0: Disable 1: SCLK0 1: Enable pin input...
  • Page 133 TMP91C829 SC1CR EVEN OERR PERR FERR SCLKS Bit symbol (0209H) R (Cleared to 0 when read.) Read/Write After reset Undefined Received Parity Parity 0: Baud rate Function 0: SCLK1 data bit8 0: Odd addition generator 1: Error 1: Even 0: Disable 1: SCLK1 1: Enable pin input...
  • Page 134 TMP91C829 − BROCR Bit symbol BR0ADDE BR0CK1 BR0CK0 BR0S3 BR0S2 BR0S1 BR0S0 (0203H) Read/Write After reset +(16 − K)/16 00: φT0 Function Received 01: φT2 data bit8 division Setting of the divided frequency 10: φT8 0: Disable 11: φT32 1: Enable +(16 −...
  • Page 135 TMP91C829 − BR1CR Bit symbol BR1ADDE BR1CK1 BR1CK0 BR1S3 BR1S2 BR1S1 BR1S0 (020BH) Read/Write After reset +(16 − K)/16 00: φT0 Function Received 01: φT2 data bit8 division Setting of the divided frequency 10: φT8 0: Disable 11: φT32 1: Enable +(16 −...
  • Page 136 TMP91C829 (Transmission) SC0BUF (0200H) (Receiving) Note: Prohibit read-modify-write for SC0BUF. Figure 3.10.13 Serial Transmission/Receiving Buffer Registers (Channel 0, SC0BUF) SC0MOD1 Bit symbol I2S0 FDPX0 STSEN0 (0205H) Read/Write After reset Function IDLE2 Duplex STS0 0: Stop 0: Half 0: Enable 1: Run 1: Full 1: Disable Figure 3.10.14 Serial Mode Control Register 1 (Channel 0, SC0MOD1)
  • Page 137 TMP91C829 3.10.4 Operation in Each Mode (1) Mode 0 (I/O interface mode) This mode allows an increase in the number of I/O pins available for transmitting data to or receiving data from an external shift register. This mode includes the SCLK output mode to output synchronous clock SCLK and SCLK input external synchronous clock SCLK.
  • Page 138 TMP91C829 Transmission In SCLK output mode 8-bit data and a synchronous clock are output on the TXD0 and SCLK0 pins respectively each time the CPU writes the data to the transmission buffer. When all the data has been output, INTES0<ITX0C> is set to 1, causing an INTTX0 interrupt to be generated.
  • Page 139 TMP91C829 Receiving In SCLK output mode the synchronous clock is output on the SCLK0 pin and the data is shifted to receiving buffer 1. This is initiated when the receive interrupt flag INTES0<IRX0C> is cleared as the received data is read. When 8-bit data is received, the data is transferred to receiving buffer 2 (SC0BUF) following the timing shown below and INTES0<IRX0C>...
  • Page 140 TMP91C829 Transmission and receiving (Full duplex mode) When full duplex mode is used, set the receive interrupt level to 0 and set enable the level of transmit interrupt. Ensure that the program which transmits the interrupt reads the receiving buffer before setting the next transmit data. The following is an example of this: Example: Channel 0, SCLK output Baud rate = 9600 bps...
  • Page 141 TMP91C829 (2) Mode 1 (7-bit UART mode) 7-bit UART mode is selected by setting the serial channel mode register SC0MOD0<SM1:0> field to 01. In this mode a parity bit can be added. Use of a parity bit is enabled or disabled by the setting of the serial channel control register SC0CR<PE>...
  • Page 142 TMP91C829 * Clock state System clock: High frequency (fc) Clock gear: 1 (fc) Prescaler clock: System clock Main settings 7 6 5 4 3 2 1 0 ← − − − − − − 0 − Set P80 to function as the TXD0 pin. P8CR ←...
  • Page 143 TMP91C829 Protocol a. Select 9-bit UART mode on the master and slave controllers. b. Set the SC0MOD0<WU> bit on each slave controller to 1 to enable data receiving. c. The master controller transmits data one frame at a time. Each frame includes an 8-bit select code which identifies a slave controller.

  • Page 144: Setting Example

    TMP91C829 Setting example: To link two slave controllers serially with the master controller using the internal clock f as the transfer clock. Master Slave 1 Slave 2 Select code Select code 00000001 00001010 Since serial channels 0 and 1 operate in exactly the same way, channel 0 only is used for the purposes of this explanation.
  • Page 145 TMP91C829 3.11 Analog/Digital Converter The TMP91C829 incorporates a 10-bit successive approximation type analog/digital converter (AD converter) with 8-channel analog input. Figure 3.11.1 is a block diagram of the AD converter. The 8-channel analog input pins (AN0 to AN7) are shared with the input-only port, port A and can thus be used as an input port. Note: When IDLE2, IDLE1 or STOP mode is selected, so as to reduce the power, with some timings the system may enter a standby mode even though the internal comparator is still enabled.
  • Page 146 TMP91C829 3.11.1 Analog/Digital Converter Registers The AD converter is controlled by the two AD mode control registers: ADMOD0 and ADMOD1. The eight AD conversion data upper and lower registers (ADREG04H/L, ADREG15H/L, ADREG26H/L, and ADREG37H/L) store the results of AD conversion. Figure 3.11.2 shows the registers related to the AD converter.
  • Page 147 TMP91C829 AD Mode Control Register 1 ADMOD1 Bit symbol VREFON I2AD ADTRGE ADCH2 ADCH1 ADCH0 (02B1H) Read/Write After reset Function VREF IDLE2 AD external Analog input channel selection. application 0: Stop trigger start control 1: Operate control 0: OFF 0: Disable 1: ON 1: Enable Analog input channel selection...
  • Page 148 TMP91C829 AD Conversion Data Lower Register 0/4 ADREG04L Bit symbol ADR01 ADR00 ADR0RF (02A0H) Read/Write After reset Undefined Function Stores lower 2 bits of AD conversion conversion result. data storage flag 1: Conversion result stored AD Conversion Data Upper Register 0/4 ADREG04H Bit symbol ADR09...
  • Page 149 TMP91C829 AD Conversion Result Lower Register 2/6 ADREG26L Bit symbol ADR21 ADR20 ADR2RF (02A4H) Read/Write After reset Undefined Function Stores lower 2 bits of AD conversion conversion result. data storage flag 1: Conversion result stored AD Conversion Data Upper Register 2/6 ADREG26H Bit symbol ADR29...
  • Page 150 TMP91C829 3.11.2 Description of Operation (1) Analog reference voltage A high-level analog reference voltage is applied to the VREFH pin; a low-level analog reference voltage is applied to the VREFL pin. To perform AD conversion, the reference voltage, the difference between VREFH and VREFL, is divided by 1024 using string resistance.
  • Page 151 TMP91C829 (4) AD conversion modes and the AD conversion end interrupt The four AD conversion modes are: • Channel fixed single conversion mode • Channel scan single conversion mode • Chanel fixed repeat conversion mode • Channel scan repeat conversion mode The ADMOD0<REPEAT>...
  • Page 152 TMP91C829 Channel scan repeat conversion mode Setting ADMOD0<REPEAT> and ADMOD0<SCAN> to 11 selects conversion channel scan repeat conversion mode. In this mode data on the specified scan channels is converted repeatedly. When each scan conversion has been completed, ADMOD0<EOCF> is set to 1 and an INTAD interrupt request is generated.
  • Page 153 TMP91C829 Table 3.11.3 Correspondence between Analog Input Channels and AD Conversion Result Registers AD Conversion Result Register Analog Input Channel Channel Fixed Repeat Conversion Modes (Port A) Conversion Mode Other than at Right (every 4 th conversion) ADREG04H/L ADREG04H/L ADREG15H/L ADREG15H/L ADREG26H/L ADREG26H/L...
  • Page 154 TMP91C829 3.12 Watchdog Timer (Runaway detection timer) The TMP91C829 features a watchdog timer for detecting runaway. The watchdog timer (WDT) is used to return the CPU to normal state when it detects that the CPU has started to malfunction (Runaway) due to causes such as noise. When the watchdog timer detects a malfunction, it generates a non-maskable interrupt INTWD to notify the CPU of the malfunction.
  • Page 155 TMP91C829 The watchdog timer consists of a 22-stage binary counter which uses the system clock ) as the input clock. The binary counter can output f WDT counter Overflow WDT interrupt Clear write code WDT clear (Soft ware) Figure 3.12.2 Normal Mode The runaway is detected when an overflow occurs, and the watchdog timer can reset device.
  • Page 156 TMP91C829 3.12.2 Control Registers The watchdog timer WDT is controlled by two control registers WDMOD and WDCR. (1) Watchdog timer mode register (WDMOD) Setting the detection time for the watchdog timer in <WDTP> This 2-bit register is used for setting the watchdog timer interrupt time used when detecting runaway.
  • Page 157 TMP91C829 − WDMOD Bit symbol WDTE WDTP1 WDTP0 I2WDT RESCR (0300H) Read/Write After reset Function WDT control Select detecting time IDLE2 1: Internally Always 1: Enable 00: 2 0: Stop connects write “0”. 1: Operate WDL out 01: 2 to the 10: 2 reset pin 11: 2...
  • Page 158 TMP91C829 3.12.3 Operation The watchdog timer generates an INTWD interrupt when the detection time set in the WDMOD<WDTP1:0> has elapsed. The watchdog timer must be zero cleared in software before an INTWD interrupt will be generated. If the CPU malfunctions (e.g., if runaway occurs) due to causes such as noise, but does not execute the instruction used to clear the binary counter, the binary counter will overflow and an INTWD interrupt will be generated.
  • Page 159 TMP91C829 3.13 Multi Vector Control 3.13.1 Multi Vector Controller (1) Outline By rewriting the value of multi vector control register (MVEC0 and MVEC1), a vector table is arbitrarily movable. (2) Control register The amount of 228 bytes become an interruption vector area from the value set as vector control register (MVEC0 and MVEC1).
  • Page 160 TMP91C829 3.13.2 Multi Boot Mode (1) Outline The TMP91C829 has multi boot mode available as an on-board programming operation mode. When in multi boot mode, the boot ROM is mapped into memory space. This boot ROM is a mask ROM that contains a program to rewrite the flash memory on board.
  • Page 161 TMP91C829 (3) Memory map Figure 3.12.2 shows memory maps for multi chip and multi boot modes. When start up in multi boot mode, internal boot ROM is mapped in FFF800H address, the boot program starts up. When start up in multi chip mode, internal boot ROM is mapped in 1F800H address, it can be made to operate arbitrarily by the user.
  • Page 162 TMP91C829 (4) SIO interface specifications The following shows the SIO communication format in multi boot mode. Before on-board programming can be executed, the communication format on the programming controller side must also be setup in the same way as for the TMP91C829.
  • Page 163 TMP91C829 Table 3.13.3 Baud Rate Modification Command Baud Rate (bps) 9600 19200 38400 57600 115200 Modification Command Table 3.13.4 Operation Command Operation Command Operation Start user program Table 3.13.5 Version Management Information Version Information ASCII code FRM1 46H, 52H, 4DH, 31H Table 3.13.6 Frequency Measurement Result Data Frequency of Resonator 16.000...
  • Page 164 TMP91C829 6. The 7th byte is used to send information of the measured frequency. The controller should check that the frequency of the resonator is measured correctly. 7. The receive data in the 8th byte is the baud rate modification data. The five kinds of baud rate modification data shown in Table 3.13.3 are available.
  • Page 165 TMP91C829 b. Error code The boot program sends the processing status to the controller using various code. The error code is listed in the table below. Table 3.13.7 Error Code Error Code Meaning of Error Code Baud rate modification error occurred. Operation command error occurred.
  • Page 166 TMP91C829 Transmit a user program not by the ASCII code but by binary. However, start mark “:” is 3AH (ASCII code). Example: Transmit data in the case of writing in 16-byte data from address 1060H Data record 3A 10 1060 00 0607F100030000F201030000B1F16010 77 Data Checksum Record type...
  • Page 167 TMP91C829 (7) Ports setup of the boot program Only ports shown in Table 3.13.9 are setup in the boot program. At the time of boot program use, be careful of the influence on a user system. Do not use space and P60 in the system which uses the boot program.

  • Page 168: Electrical Characteristics

    TMP91C829 Electrical Characteristics Maximum Ratings Parameter Symbol Rating Unit −0.5 to 5.75 Power supply voltage (5 V) HVcc −0.5 to 4.0 Power supply voltage (3 V) LVcc −0.5 to Vcc + 0.5 Input voltage Output current (Per pin) −2 Output current (Per pin) ΣIOL Output current (Total) ΣIOH...
  • Page 169 TMP91C829 DC Characteristics (1/2) Parameter Symbol Condition Typ. (Note) Unit Power supply voltage (5 V) (AVcc = HVcc) fc = 10 to 36 MHz HVCC 4.75 5.25 (AVss = DVss = 0 V) fc = 10 to 36 MHz Power supply voltage (3 V) LVCC D0 to D7, P10 to P17 (D8 to D15)
  • Page 170 TMP91C829 AC Characteristics (1) HVcc = 5.0 V ± 5%, LVcc = 3.0 to 3.6 V = 36 MHz Variable Parameter Symbol Unit period ( = x ) 27.6 27.6 A0 to A23 valid → x − 26 fall rise → A0 to A23 hold 0.5x −...
  • Page 171 Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative. 2006-03-15 91C829-169...

  • Page 172: Write Cycle

    Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative. 2006-03-15 91C829-170...

  • Page 173: Ad Conversion Characteristics

    TMP91C829 AD Conversion Characteristics AVcc = HVcc, AVss = Vss Parameter Symbol Typ. Unit − 0.2 V Analog reference voltage ( + ) VREFH Analog reference voltage ( − ) DVss + 0.2 V VREFL Analog input voltage range VAIN REFL REFH Analog current for analog...
  • Page 174 TMP91C829 Serial Channel Timing (I/O internal mode) Note: Symbol “x” in the above table means the period of clock “f ”, it’s half period of the system clock “f ” for CPU core. The period of f depends on the clock gear setting. (1) SCLK input mode 36 MHz Variable...
  • Page 175 TMP91C829 Event Counter (TA0IN, TA4IN, TB0IN0, TB0IN1) Variable 36 MHz Parameter Symbol Unit 8X + 100 Clock perild 4X + 40 Clock low level width VCKL 4X + 40 Clock high level width VCKH Note: Symbol “x” in the above table means the period of clock “f ”, it’s half period of the system clock “f ”...
  • Page 176 TMP91C829 Bus Request/Bus Acknowledge BUSRQ (Note 1) CBAL BUSAK (Note 2) D0 to D15 A0 to A23, (Note 2) = 36 MHz Variable Parameter Symbol Unit Output buffer to BUSAK high to output buffer on BUSAK Note 1: Even if the signal goes low, the bus will not be released while the signal is low.
  • Page 177 TMP91C829 Table of SFRs The special function registers (SFRs) include the I/O ports and peripheral control registers allocated to the 4-Kbyte address space from 000000H to 000FFFH. (1) I/O port (2) I/O port control (3) Interrupt control (4) Chip select/wait control (5) Clock gear (6) 8-bit timer (7) 16-bit timer...
  • Page 178 TMP91C829 Table 5.1 Address Map SFRs [1] PORT Address Name Address Name Address Name 0000H 0010H P5CR 0020H 1H P1 1H P5FC 2H P6 3H P7 4H P1CR 4H P6CR 5H P6FC 6H P2 6H P7CR 7H P7FC 8H P8 9H P2FC 9H P9 AH P8CR...
  • Page 179 TMP91C829 [3] CS/WAIT [4] CGEAR, DFM Address Name Address Name 00C0H B0CS 00E0H SYSCR0 1H B1CS 1H SYSCR1 2H B2CS 2H SYSCR2 3H B3CS 3H EMCCR0 4H EMCCR1 7H BEXCS 8H MSAR0 9H MAMR0 AH MSAR1 BH MAMR1 CH MSAR2 DH MAMR2 EH MSAR3 FH MAMR3...
  • Page 180 TMP91C829 [6] TMRB [7] UART/SIO Address Name Address Name 0180H TB0RUN 0200H SC0BUF SC0CR 2H TB0MOD SC0MOD0 3H TB0FFCR BR0CR BR0ADD SC0MOD1 8H TB0RG0L SC1BUF 9H TB0RG0H SC1CR AH TB0RG1L SC1MOD0 BH TB0RG1H BR1CR CH TB0CP0L BR1ADD DH TB0CP0H SC1MOD1 EH TB0CP1L FH TB0CP1H [8] 10-Bit ADC...
  • Page 181 TMP91C829 (1) I/O port Symbol Name Address Port 1 Data from external port (Output latch register is cleared to 0.) Port 2 R/W* Port 5 Data from external port (Output latch register is set to 1.) 0(Output latch register): Pull-up resistor OFF 1(Output latch register): Pull-up resistor ON Port 6 Port 7...
  • Page 182 TMP91C829 (2) I/O port control (1/2) Symbol Name Address P17C P16C P15C P14C P13C P12C P11C P10C Port 1 P1CR (Prohibit control RMW) 0: Input 1: Output P27F P26F P25F P24F P23F P22F P21F P20F Port 2 P2FC (Prohibit function RMW) 0: Port 1: Address bus (A23 to A16) P56C...
  • Page 183 TMP91C829 I/O port control (2/2) Symbol Name Address P96C P95C P94C P93C P90C Port 9 P9CR (Prohibit control RMW) 0: Input 0: Input 1: Output 1: Output P96F P95F P90F Port 9 P9FC (Prohibit function RMW) 0: Port 0: Port 0: Port 1: TB0OUT0 1: TB0OUT1...

  • Page 184: Interrupt Control

    TMP91C829 (3) Interrupt control (1/3) Symbol Name Address INTAD INT0 Interrupt IADC IADM2 IADM1 IADM0 I0M2 I0M1 I0M0 INTE0AD enable 0 & AD Interrpt request level Interrpt request level 1: INTAD 1: INT0 INT2 INT1 Interrupt I2M2 I2M1 I2M0 I1M2 I1M1 I1M0 enable...
  • Page 185 TMP91C829 Interrupt control (2/3) Symbol Name Address INTTX0 INTRX0 Interrupt ITX0C ITX0M2 ITX0M1 ITX0M0 IRX0C IRX0M2 IRX0M1 IRX0M0 INTES0 enable serial 0 1: INTTX0 Interrpt request level 1: INTRX0 Interrpt request level INTTX1 INTRX1 Interrupt ITX1C ITX1M2 ITX1M1 ITX1M0 IRX1C IRX1M2 IRX1M1 IRX1M0...
  • Page 186 TMP91C829 Interrupt control (3/3) Symbol Name Address DMA0V5 DMA0V4 DMA0V3 DMA0V2 DMA0V1 DMA0V0 DMA 0 request DMA0V vector DMA0 start vector DMA1V5 DMA1V4 DMA1V3 DMA1V2 DMA1V1 DMA1V0 DMA 1 request DMA1V vector DMA1 start vector DMA2V5 DMA2V4 DMA2V3 DMA2V2 DMA2V1 DMA2V0 DMA 2 request...
  • Page 187 TMP91C829 (4) Chip select/wait control (1/2) Symbol Name Address B0OM1 B0OM0 B0BUS B0W2 B0W1 B0W0 Block 0 CS/WAIT B0CS 0: Disable 00: ROM/SRAM Data bus 000: 2 waits control (Prohibit 1: Enable width 001: 1 wait register RMW) 010: (1 + N) waits 1xx: Reserved Reserved 0: 16 bits 1: 8 bits...
  • Page 188 TMP91C829 Chip select/wait control (2/2) Symbol Name Address Memory start MSAR2 address register 2 Start address A23 to A16 Memory address MAMR2 mask register 2 CS2 area size 0: Enable address comparsion Memory start MSAR3 address register 3 Start address A23 to A16 Memory address MAMR3...
  • Page 189 TMP91C829 (5) Clock gear Symbol Name Address − − − − − WUEF PRCK1 PRCK0 Warm-up Always Always Always Always Always Prscaler clock seleciton timer write “1”. write “0”. write “1”. write “0”. write “0”. 00: f System 0 Write: 01: Reserved clock Don’t care...
  • Page 190 TMP91C829 (6) 8-bit timer (1/2) (6−1) TMRA01 Symbol Name Address TA0RDE I2TA01 TA01PRUN TA1RUN TA0RUN 8-bit TA01RUN timer 100H Double IDLE2 8-bit timer run/stop control buffer 0: Stop 0: Stop and clear 0: Disable 1: Operate 1: Run (Count up) 1: Enable −...
  • Page 191 TMP91C829 8-bit timer (2/2) (6-3) TMRA45 Symbol Name Address TA4RDE I2TA45 TA45PRUN TA5RUN TA4RUN 8-bit TA45RUN timer 110H Double IDLE2 8-bit timer run/stop control buffer 0: Stop 0: Stop and clear 0: Disable 1: Operate 1: Run (Count up) 1: Enable −...
  • Page 192 TMP91C829 (7) 16-bit timer (1/2) (7-1) TMRB0 Symbol Name Address − TB0RDE I2TB0 TB0PRUN TB0RUN 8-bit TB0RUN 180H timer Double Always IDLE2 16-bit timer run/stop control buffer write “0”. 0: Stop 0: Stop and clear control 0: Disable 1: Operate 1: Run (Count up) 1: Enable TB0CT1...
  • Page 193 TMP91C829 (8) UART/serial channel (8-1) UART/SIO Channel 0 Symbol Name Address Serial 200H RB7/TB7 RB6/TB6 RB5/TB5 RB4/TB4 RB3/TB3 RB2/TB2 RB1/TB1 RB0/TB0 SC0BUF channel 0 (Prohibit R (Receiving)/W (Transmission) buffer RMW) Undefined EVEN OERR PERR FERR SCLKS R (Cleared to 0 by reading.) Serial Undefined SC0CR...
  • Page 194 TMP91C829 (8-2) UART/SIO channel 1 Symbol Name Address Serial 208H RB7/TB7 RB6/TB6 RB5/TB5 RB4/TB4 RB3/TB3 RB2/TB2 RB1/TB1 RB0/TB0 SC1BUF channel 1 (Prohibit R (Receiving)/W (Transmission) buffer RMW) Undefined EVEN OERR PERR FERR SCLKS R (cleared to 0 by reading.) Serial Undefined SC1CR channel 1...
  • Page 195 TMP91C829 (9) AD converter Symbol Name Address − − EOCF ADBF ITM0 REPEAT SCAN ADMOD0 MODE 2B0H 1: End 1: Busy Always Always Interrupt in 1: Repeat 1: Scan 1: Start register 0 write “0”. write “0”. repeat mode. VREFON I2AD ADTRGE ADCH2...
  • Page 196 TMP91C829 (10) Watchdog timer Symbol Name Address − WDTE WDTP1 WDTP0 I2WDT RESCR 1: WDT 00: 2 IDLE2 RESET Always WDMOD MODE 300H enable 0: Abort connect write “0”. 01: 2 register 1: Operate internally 10: 2 WDT out to 11: 2 reset pin −...
  • Page 197 TMP91C829 Port Section Equivalent Circuit Diagrams • Reading the circuit diagrams The gate symbols used are essentially the same as those used for the standard CMOS logic IC [74HCXX] series. The dedicated signal is described below. STOP: This signal becomes active (1) when the HALT mode setting register is set to STOP mode (e.g., when SYSCR2<HALTM1:0>...
  • Page 198 TMP91C829 P53 to P55, P80 to P87, PZ2, PZ3 Output data Vcc Programmable Output enable pull-up resistor STOP Input data Input enable PA (AN0 to AN7) Analog input channel select Analog input Input Input data Input enable P56 (INT0), P70 (INT1), P72 (INT2), P73 (INT3), P75 (INT4), P90 (INT5) Output data Output enable STOP...
  • Page 199 TMP91C829 AM0 to AM1 Input data Input RESET P-ch Input Reset Schmitt trigger WDTOUT Reset enable X1 and X2 Oscillator P-ch N-ch High-frequency Oscillation enable Clock VREFH and VREFL VREFON P-ch VREFH String resistor VREFL 2006-03-15 91C829-197...
  • Page 200 TMP91C829 Points to Note and Restrictions (1) Notation The notation for built-in/I/O registers is as follows register symbol <Bit symbol> (e.g., TA01RUN<TA0RUN> denotes bit TA0RUN of register TA01RUN). Read-modify-write instructions An instruction in which the CPU reads data from memory and writes the data to the same memory location in one instruction.
  • Page 201 TMP91C829 (2) Points to note AM0 and AM1 pins Fix these pins to V unless changing voltage. EMU0 and EMU1 Open pins. Reserved address areas The TMP91C829 does not have any reserved areas. HALT mode (IDLE1) When IDLE1 mode is used (in which oscillator operation only occurs), set RTCCR<RTCRUN>...
  • Page 202 TMP91C829 Releasing the HALT mode by requesting an interruption Usually, interrupts can release all halts status. However, the interrupts ( , INT0 to INT4) which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 5 clocks of f ) with IDLE1 or STOP mode (IDLE2 is not applicable to this case).

  • Page 203: Package Dimensions

    TMP91C829 8. Package Dimensions P-LQFP100-1414-0.50F Unit: mm 2006-03-15 91C829-201...
  • Page 204 TMP91C829 2006-03-15 91C829-202...

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