Page 1 Data Book 32bit Micro controller TLCS-900/H1 series TMP92CH21FG TENTATIVE Rev0.92 11th/Jul./2002 Since this Revision 0.92 is still under working, there may be some mistakes in it. When you will start to design, please order the latest one.
Page 2: Table Of Contents
--------- Contents-------- Outline and Device Characteristics ･･･････････････････････ 92CH21-1 Pin Assignment and Functions ････････････････････････ 92CH21-5 2.1 Pin Assignment ･･･････････････････････････････････ 92CH21-5 2.2 Pin name and functions ････････････････････････････ 92CH21-6 Oepration ･･･････････････････････････････････････････...
Page 3 3.18 16-bit Timers (TMRB) ･････････････････････････････ 92CH21-385 3.19 Touch Screen interface･････････････････････････････ 92CH21-395 ･･････････････････････････ 3.20 I 92CH21-401 ･･････････････････････････ 3.21 Boot ROM 92CH21-408 3.22 Power Supply Backup ････････････････････ 92CH21-426 Electrical Charactoristics ･･･････････････････････････････ 92CH21-428 Table of Speial function registers (SFRs) ･････････････････ 92CH21-449 Package ･････････････････････････････････････ 92CH21-492 ...
Page 4 DataBook Modification History Rev/Data Page Modification item Reason 0.91 New release /20-Apr-2002 0.92 1,3,6 Product name : JTMP92CH21 explanation New added /10-Jul-2002 4,7,431 Modified Pin assignment for S0ALEL/H,S1ALEL/H Mistake Deleted Port0 in Pin assignment (Shown by Modified attribute(I/O) for MX,MY Blue-color) Modified Figure 3.1 Separated Figure 3.5.11...
Page 5: Outline And Device Characteristics
It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications.
Page 6 Under Development TMP92CH21 (8) General-purpose serial interface: 2 channels •UART/Synchronous mode: 2 channels (ch.0 and 1) •IrDA Ver.1.0(115kbps) mode selectable: 1channel (ch.0) (9) USB(Universal Serial Bus) Controller : 1 channel •Compliant with USB rev1.1 •Full-speed (12MHz) (LOW-spped is not supported.) •Endpoints spec Endpoint-0 : Control 64Bytes*1 -FIFO...
Page 7 •VCC = 3.0 V to 3.6 V (fc max = 40MHz) •VCC = 2.7 V to 3.6 V (fc max = 27MHz) (27) Package: •144-pin QFP (P-LQFP144 -1616 - 0.40) •144-pin Chip form is also available. For details, contact your local Toshiba sales representative. 92CH21 - 3...
Page 8 Under Development TMP92CH21 DVCC[3],RTCVCC PG0 to PG1 DVSS[3] (AN0 to AN1) 10-bit 4ch 900/H1 CPU AN2/MX(PG2) AN3/MY/ADTRG(PG3) H-OSC AVCC,AVSS Converter Clock Gear VREFH,VREFL (PX,INT4)P96 Touch Screen (PY,INT5)P97 L-OSC I/F(TSI) /RESET (TXD0,TXD1)PF0 SERIAL I/O (RXD0,RXD1)PF1 SIO0 (SCLK0,/SCLK0)PF2 INTERRUPT Controller SERIAL I/O SIO1 (D0 to D7) PORT0...
Page 9: Pin Assignment And Functions
TMP92CH21 2. Pin Assignment and Functions The assignment of input/output pins for the TMP92CH21FG, their names and functions are as follows: 2.1 Pin Assignment P67,A23 VREFL VREFH P66,A22 PG0,AN0 P65,A21 PG1,AN1 P64,A20 PG2,AN2,MX DVCC3 P63,A19 PG3,AN3,/ADTRG,MY P62,A18 P96,PX,INT4 P61,A17 P97,PY,INT5 PA3,KI3,LD8 P60,A16 PA4,KI4,LD9...
Page 10 TMP92CH21 2.2 PAD Assignment (Chip size 5.98mm × 6.42mm) Table2.2.1 Pad assignment diagram (144-pin chip) Unit: μm Name X point Y point Name X point Y point Name X point Y point -2852 2671 DVSS2 -488 -3072 2848 VREFL -2852 2546 DVCC2 -338...
Page 11: Pin Name And Functions
TMP92CH21 2.3 Pin names and functions The following table shows the names and functions of the input/output pins Table2.3.1 Pin names and functions (1/5) Number of Pin Name Function pins D0 to D7 Data: Data bus 0 to 7 P10 to P17 Port 1: I/O port Input or output specifiable in units of bits D8 to D15 Data: Data bus 8 to 15...
Page 12 TMP92CH21 Table2.3.1 Pin names and functions (2/5) Number of Pin Name Function pins Output Port80:Output port /CS0 Output Chip select 0: Outputs “Low” when address is within specified address area Output Port81:Output port /CS1 Output Chip select 1: Outputs “Low” when address is within specified address area /SDCS Output Chip Select for SDRAM: Outputs “0”...
Page 13 TMP92CH21 Table2.3.1 Pin names and functions (3/5) Number of Pin Name Function pins PortC0: I/O port INT0 Input Interrupt request pin0 : Interrupt request pin with programmable level / rising /falling edge TA1OUT Output 8bit timer 1 output: Timer 1 output PortC1: I/O port INT1 Input...
Page 14 TMP92CH21 Table2.3.1 Pin names and functions (4/5) Number of Pin Name Function pins Output PortJ0: Output port /SDRAS Output Row Address Storobe for SDRAM /SRLLB Output Data enable for SRAM on pins D0 to D7 Output PortJ1: Output port /SDCAS Output Column Address Storobe for SDRAM /SRLUB...
Page 15 TMP92CH21 Table2.3.1 Pin names and functions (5/5) Number of Pin Name Function pins D+, D- USB-data Connecting pin Operation mode: Fix to AM1=”0”,AM0=”1” for 16-bit external bus starting AM0,AM1 Fix to AM1=”1”,AM0=”0” for 32-bit external bus starting Fix to AM1=”1”,AM0=”1” for BOOT(32-bit internal-MROM ) starting X1/X2 High-frequency oscillator connection pins XT1/XT2...
Page 16: Cpu
TMP92CH21 OPERATION This section describes the basic components, functions and operation of the TMP92CH21. 3.1 CPU The TMP92CH21 contains an advanced high-speed 32-bit CPU(900/H1 CPU) 3.1.1 CPU Outline 900/H1 CPU is high-speed and high-performance CPU based on 900/L1 CPU. 900/H1 CPU has expanded 32-bit internal data bus to process Instructions more quickly.
Page 17 TMP92CH21 Bank 0). When the Reset is released, the CPU starts executing instructions according to the Program Counter settings. CPU internal registers not mentioned above do not change when the Reset is released. When the Reset is accepted, the CPU sets internal I/O, ports and other pins as follows. •...
Page 18: Memory Map
TMP92CH21 3.2 Memory Map Figure 3.2 is a memory map of the TMP92CH21. 000000H Internal I/O Direct area (n) (8 KByte) 000100H 001D00H 64Kbyte area 002000H (nn) Internal RAM (16 KByte) 006000H 010000H 3FE000H BOOT(Internal MROM) (Note1) (8 KByte) 400000H External memory 16Mbyte area...
Page 19: Clock Function And Standby Function
TMP92CH21 3.3 Clock Function and Standby Function TMP92CH21 contains (1)clock gear, (2)clock doubler(PLL), (3) standby controller and (4) noise-reducing circuit. They are used for low-power, low-noise systems. This chapter is organized as follows: 3.3.1 Block diagram of system clock 3.3.2 SFRs 3.3.3 System clock controller 3.3.4 Prescaler clock controller 3.3.5 Noise-reducing circuit...
Page 20 TMP92CH21 The clock operating modes are as follows: (a) Single Clock Mode (X1, X2 pins only), (b) Dual Clock Mode (X1, X2, XT1 and XT2 pins) and (c) Triple Clock Mode (X1, X2, XT1 and XT2 pins and PLL). Figure 3.3.1 shows a transition figure. Reset /32) OSCH...
Page 21 TMP92CH21 3.3.1 Block diagram of system clock SYSCR0<WUEF> SYSCR2<WUPTM1 to 0> Warming up timer φT (High/Low frequency oscillator) φT0 Lock up timer ÷4 ÷8 (PLL) SYSCR0<XTEN > PLLCR1<PLLON>, PLLCR0<LUPFG> Low-Frequency oscillator ÷2 fc/2 ÷2 × 4 OSCH fc/4 fc/8 SYSCR1<SYSCK> SYSCR0<XEN >...
Page 22 TMP92CH21 3.3.2 SFR SYSCR0 bit Symbol XTEN WUEF (10E0H) Read/Write After reset High-frequen Low-frequen Warm-up cy oscillator cy oscillator Timer (fc) (fs) 0: Write 0: Stop 0: Stop Don’t care 1: Oscillation 1: Oscillation 1: Write start timer Function 0: Read end warm-up 1: Read do not end...
Page 23 TMP92CH21 EMCCR0 bit symbol PROTECT EXTIN DRVOSCH DRVOSCL (10E3H) Read/Write After reset Protect flag 1: External fc oscillator fs oscillator 0: OFF clock driverability driverability Function 1: ON 1: NORMAL 1: NORMAL 0: WEAK 0: WEAK EMCCR1 bit symbol (10E4H) Read/Write Switching the protect ON/OFF by write to following 1 -KEY,2...
Page 24 TMP92CH21 PLLCR0 bit symbol FCSEL LUPFG (10E8H) Read/Write After reset Select fc-clock Lock-up timer 0 : f Status flag OSCH Function 1 : f 0 : not end 1 : end (Note) Be carefull that logic of PLLCR0<LUPFG> is different from 900/L1’s DFM. PLLCR1 bit symbol PLLON...
Page 25 TMP92CH21 3.3.3 System clock controller The system clock controller generates the system clock signal (f ) for the CPU core and internal I/O. It contains two oscillation circuits and a clock gear circuit for high-frequency (fc) operation. The register SYSCR1<SYSCK> changes the system clock to either fc or fs, SYSCR0<XEN>...
Page 26 TMP92CH21 Example 1-Setting the clock Changing from high frequency (fc) to low frequency (fs). SYSCR0 10E0H SYSCR1 10E1H SYSCR2 10E2H (SYSCR2), 0X11−−XXB Sets warm-up time to 2 /fs. 6, (SYSCR0) Enables low-frequency oscillation. 2, (SYSCR0) Clears and starts warm-up timer. WUP: 2, (SYSCR0) Detects stopping of warm-up timer.
Page 27 TMP92CH21 Example 2-Setting the clock Changing from low frequency (fs) to high frequency (fc). SYSCR0 10E0H SYSCR1 10E1H SYSCR2 10E2H (SYSCR2), 0X10−−XXB Sets warm-up time to 2 /fc. 7, (SYSCR0) Enables high-frequency oscillation. 2, (SYSCR0) Clears and starts warm-up timer. WUP: 2, (SYSCR0) Detects stopping of warm-up timer.
Page 28 TMP92CH21 (2) Clock gear controller is set according to the contents of the Clock Gear Select Register SYSCR1<GEAR2 to 0> to either fc, fc/2, fc/4, fc/8 or fc/16. Using the clock gear to select a lower value of f reduces power consumption. Example 3 Changing to a high-frequency gear SYSCR1...
Page 29 TMP92CH21 3.3.4 Clock doubler (PLL) PLL outputs the f clock signal, which is four times as fast as f . It can use the OSCH low-frequency oscillator, even though the internal clock is high-frequency. A Reset initializes PLL to Stop status, setting to PLLCR0,PLLCR1-register is needed before use.
Page 30 TMP92CH21 Limitation point on the use of PLL 1. It’s prohibited to execute PLL enable/disable control in the SLOW mode(fs) (writing to PLLCR0 and PLLCR1). You should control PLL in the NORMAL mode. 2. If you stop PLL operation during using PLL , you should execute following setting in the same order.
Page 31 TMP92CH21 (2) Change / Stop Control (OK) PLL use mode (f )→ High frequency oscillator operation mode(f )→ PLL Stop OSCH → Low frequency oscillator operation mode(f )→High frequency oscillator stop (PLLCR0),-0------B ; Change the system clock f to f OSCH (PLLCR1),0-------B ;...
Page 32 TMP92CH21 3.3.5 Noise reduction circuits Noise reduction circuits are built in, allowing implementation of the following features. (1) Reduced drivability for high-frequency oscillator (2) Reduced drivability for low-frequency oscillator (3) Single drive for high-frequency oscillator (4) SFR protection of register contents (1) Reduced drivability for high-frequency oscillator (Purpose) Reduces noise and power for oscillator when a resonator is used.
Page 33 TMP92CH21 (2) Reduced drivability for low-frequency oscillator (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) XT1 pin Enable oscillation Resonator EMCCR0<DRVOSCL> XT2 pin (Setting method) The drivability of the oscillator is reduced by writing 0 to the EMCCR0<DRVOSCL> register.
Page 34 TMP92CH21 (4) Runaway provision with SFR protection register (Purpose) Provision in runaway of program by noise mixing. Write operation to specified SFR is prohibited so that provision program in runaway prevents that it is it in the state which is fetch impossibility by stopping of clock, memory control register (Memory controller, MMU) is changed.
Page 35 TMP92CH21 3.3.6 Standby controller (1) Halt Modes and Port Drive-register When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1 or STOP Mode, depending on the contents of the SYSCR2<HALTM1 to 0> register and each pin-status is set according to PxDR-register. PxDR bit symbol Px7D...
Page 36 TMP92CH21 The operation of each of the different Halt Modes is described in Table 3.3.3. Table 3.3.4 I/O operation during Halt Modes Halt Mode IDLE2 IDLE1 STOP SYSCR2 <HALTM1 to 0> Stop I/O ports Depend on PxDR-register setting TMRA,TMRB Available to select Block operation block A/D converter...
Page 37 TMP92CH21 Table 3.3.5 Source of Halt state clearance and Halt clearance operation Interrupt Enabled Interrupt Disabled Status of Received Interrupt (interrupt level) ≥ (interrupt mask) (interrupt level) < (interrupt mask) Halt mode IDLE2 IDLE1 STOP IDLE2 IDLE1 STOP × − −...
Page 38 TMP92CH21 (3) Operation ① IDLE2 Mode In IDLE2 Mode only specific internal I/O operations, as designated by the IDLE2 Setting Register, can take place. Instruction execution by the CPU stops. Figure 3.3.5 illustrates an example of the timing for clearance of the IDLE2 Mode Halt state by an interrupt.
Page 39 TMP92CH21 ③ STOP Mode When STOP Mode is selected, all internal circuits stop, including the internal oscillator. After STOP Mode has been cleared system clock output starts when the warm-up time has elapsed, in order to allow oscillation to stabilize. Figure 3.3.7 illustrates the timing for clearance of the STOP Mode Halt state by an interrupt.
Page 40: Interrupts
TMP92CH21 3.4 Interrupts Interrupts are controlled by the CPU Interrupt Mask Register <IFF2 to 0> (bits 12 to 14 of the Status Register) and by the built-in interrupt controller. The TMP92CH21 has a total of 51 interrupts divided into the following five types: Interrupts generated by CPU: 9 sources •...
Page 41 TMP92CH21 In addition to the general-purpose Interrupt Processing Mode described above, there is also a Micro DMA Processing Mode. In Micro DMA Mode the CPU automatically transfers data in one-byte, two-byte or four-byte blocks; this mode allows high-speed data transfer to and from internal and external memory and internal I/O ports.
Page 42 TMP92CH21 3.4.1 General-purpose interrupt processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. However, in the case of software interrupts and Illegal Instruction interrupts generated by the CPU, the CPU skips steps ! and " and executes only steps #, $ and %. The CPU reads the interrupt vector from the interrupt controller.
Page 43 TMP92CH21 Table 3.4.1 TMP92CH21 interrupt vectors and micro DMA start vectors Default Type Interrupt Source and Source of Vector Value Address refer Micro Priority Micro DMA Request Vector Start Vector Reset or [SWI0] instruction 0000H FFFF00H [SWI1] instruction 0004H FFFF04H Illegal instruction or [SWI2] instruction 0008H FFFF08H...
Page 44 TMP92CH21 (reserved) 00C8H FFFFC8H INTAD: AD conversion end 00CCH FFFFCCH INTTC0: Micro DMA end (Channel 0) 00D0H FFFFD0H INTTC1: Micro DMA end (Channel 1) 00D4H FFFFD4H INTTC2: Micro DMA end (Channel 2) 00D8H FFFFD8H INTTC3: Micro DMA end (Channel 3) 00DCH FFFFDCH Maskable...
Page 45 TMP92CH21 3.4.2 Micro DMA processing In addition to general-purpose interrupt processing, the TMP92CH21 also includes a micro DMA function. Micro DMA processing for interrupt requests set by micro DMA is performed at the highest priority level for maskable interrupts (level 6), regardless of the priority level of the interrupt source.
Page 46 TMP92CH21 Although the control registers used for setting the transfer source and transfer destination addresses are 32 bits wide, this type of register can only output 24-bit addresses. Accordingly, micro DMA can only access 16 Mbytes (the upper eight bits of a 32-bit address are not valid). Three micro DMA transfer modes are supported: one-byte transfers, two-byte (one-word) transfer and four-byte transfer.
Page 47 TMP92CH21 (2)Soft start function The TMP92CH21 can initiate micro DMA either with an interrupt or by using the micro DMA soft start function, in which micro DMA is initiated by a Write cycle which writes to the register DMAR. Writing 1 to any bit of the register DMAR causes micro DMA to be performed once. On completion of the transfer, the bits of DMAR which support the end channel are automatically cleared to 0.
Page 48 TMP92CH21 (4)Detailed description of the Transfer Mode Register Mode DMAM0 to 7 Execution DMAMn[4:0] Mode Description State number 0 0 0 z z Destination INC mode (DMADn +) ← (DMASn) 5states DMACn ← DMACn - 1 if DMACn = 0 then INTTCn 0 0 1 z z Destination DEC mode (DMADn -) ←...
Page 49 TMP92CH21 3.4.3 Interrupt controller operation The block diagram in Figure 3.4.3 shows the interrupt circuits. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit. For each of the 52 interrupt channels there is an interrupt request flag (consisting of a flip-flop), an interrupt priority setting register and a micro DMA start vector register.
Page 50 Interrupt controller Interrupt request F/F 1 RESET interrupt Interrupt RESET vector read V = 20H mask F/F INTWD V = 24H Interrupt request Decoder Priority setting register Priority encoder EI 1 IFF2 to 0 signal to CPU Dn + 1 ...
Page 51 TMP92CH21 (1) Interrupt level setting registers Symbol NAME Address INTAD INT0 INT0 & INTAD IADC IADM2 IADM1 IADM0 I0M2 I0M1 I0M0 INTE0AD Enable INT2 INT1 INT1 & INT2 I2M2 I2M1 I2M0 I1M2 I1M1 I1M0 INTE12 Enable INT4 INT3 INT3 & INT4 I4M2 I4M1 I4M0...
Page 52 TMP92CH21 Symbol NAME Address INTALM4 INTEALM INTALM4 IA4C IA4M2 IA4M1 IA4M0 Enable Note: Always fixed to 0 INTRTC INTRTC IRM2 IRM1 IRM0 INTERTC Enable Note: Always fixed to 0 INTKEY INTEC INTKEY IKM2 IKM1 IKM0 Enable Note: Always fixed to 0 INTLCD INTLCD ILCD1C ILCDM2 ILCDM1 ILCDM0...
Page 53 TMP92CH21 Symbol NAME Address INTTC1(DMA1) INTTC0(DMA0) INTTC0 & INTTC1 ITC1C ITC1M2 ITC1M1 ITC1M0 ITC0C ITC0M2 ITC0M1 ITC0M0 INTETC01 Enable INTTC3(DMA3) INTTC2(DMA2) INTTC2& INTTC3 ITC3C ITC3M2 ITC3M1 ITC3M0 ITC2C ITC2M2 ITC2M1 ITC2M0 INTETC23 Enable INTTC5(DMA5) INTTC4(DMA4) INTTC4 & INTTC5 ITC5C ITC5M2 ITC5M1 ITC5M0 ITC4C...
Page 54 TMP92CH21 External interrupt control NAME Address Symbol I5EDGE I4EDGE I3EDGE I2EDGE I1EDGE I0EDGE I0LE Interrupt Input IIMC INT5EDGE INT4EDGE INT3EDGE INT2EDGE INT1EDGE INT0EDGE 0:INT0 Write “0” Mode RMW) 0: Rising 0: Rising 0: Rising 0: Rising 0: Rising 0: Rising edge mode Control 1: Falling...
Page 55 TMP92CH21 SIO Receive interrupt control Symbol NAME Address IR1LE IR0LE Write ‘0’ 0:INTRX1 0:INTRX0 Interrupt SIMC edge edge Mode (no RMW) mode mode Control 1:INTRX1 1:INTRX0 level level mode mode INTRX1 Level Enable Rising edge detect INTRX1 “H”level INTRX1 INTRX0 rising edge Enable Rising edge detect INTRX0 “H”level INTRX0 92CH21 - 51...
Page 56 TMP92CH21 (4) Interrupt request flag clear register The interrupt request flag is cleared by writing the appropriate micro DMA start vector, as given in Table 3.4 (1), to the register INTCLR. For example, to clear the interrupt flag INT0, perform the following register operation after execution of the DI instruction.
Page 57 TMP92CH21 Symbol NAME Address DMA0 Start Vector DMA0 DMA0V5 DMA0V4 DMA0V3 DMA0V2 DMA0V1 DMA0V0 DMA0V Start 100h Vector DMA1 Start Vector DMA1 DMA1V5 DMA1V4 DMA1V3 DMA1V2 DMA1V1 DMA1V0 DMA1V Start 101h Vector DMA2 Start Vector DMA2 DMA2V5 DMA2V4 DMA2V3 DMA2V2 DMA2V1 DMA2V0 DMA2V...
Page 58 TMP92CH21 (6) Specification of a micro DMA burst Specifying the micro DMA burst function causes micro DMA transfer, once started, to continue until the value in the Transfer Counter Register reaches zero. Setting any of the bits in the register DMAB which correspond to a micro DMA channel (as shown below) to 1 specifies that any micro DMA transfer on that channel will be a burst transfer.
Page 59 TMP92CH21 (7)Notes The instruction execution unit and the bus interface unit in this CPU operate independently. Therefore if, immediately before an interrupt is generated, the CPU fetches an instruction which clears the corresponding interrupt request flag, the CPU may execute this instruction in between accepting the interrupt and reading the interrupt vector.
Page 60: Function Of Ports
TMP92CH21 3.5 Function of Ports TMP92CH21 has I/O port pins that are shown in table 3.5.1 In addition to functioning as general-purpose I/O ports, these pins are also used by internal CPU and I/O functions. Table 3.5.2 lists I/O registers and their specifications.
Page 61 TMP92CH21 Table 3.5.1 Port Functions (2/2) (R: PU= with programmable pull-up resistor, PD= with programmable pull-down resistor,U= with pull-up resistor) Number of Port Name Pin Name I/O Setting Pin Name for built-in function Pins − PG0 to PG1 Input (Fixed) AN0 to...
Page 62 TMP92CH21 Table 3.5.2 I/O Registers and Specifications (1/3) X: Don’t care I/O register Port Pin name Specification PnCR PnFC PnFC2 Port 1 P10 to P17 Input port None Output port D8 to D15 bus Port 2 P20 to P27 Input port Output port D16 to D23 bus KO0 to KO7...
Page 63 TMP92CH21 Table 3.5.2 I/O Registers and Specifications (2/3) X: Don’t care I/O register Port Pin name Specification PnCR PnFC PnFC2 Port 9 Input port P90 to P97 P90 to P95 Output port TXD0 output I2SCKO output TXD0 output(Open Drain) RXD0 input I2SDO output SCLK0 output I2SWS output...
Page 64 TMP92CH21 Table 3.5.2 I/O Registers and Specifications (3/3) X: Don’t care Port Pin name I/O register Specification PnCR PnFC PnFC2 Port G PG0 to PG3 Input port AN0 to AN3 input /ADTRG input None None None MX output MY outout Port J PJ0 to PJ7 Output port...
Page 65 TMP92CH21 3.5.1 Port 1 (P10 to P17) Port1 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P1CR and function register P1FC. In addition to functioning as a general-purpose I/O port, port1 can also function as a data bus (D8 to D15). Function Setting after reset is released Don’t use this setting Data Bus (D8 to D15)
Page 66 TMP92CH21 3.5.2 Port 2 (P20 to P27) Port2 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P2CR and function register P2FC. In addition to functioning as a general-purpose I/O port, port2 can also function either as a data bus (D16 to D23) or key-board interface pin KO0 to KO7 which can set to open drain output buffer.
Page 67 TMP92CH21 3.5.3 Port 3 (P30 to P37) Port3 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P3CR and function register P3FC. In addition to functioning as a general-purpose I/O port, port3 can also function either as a data bus (D24 to D31) Function Setting after reset is released Don’t use this setting...
Page 68 TMP92CH21 3.5.4 Port 4 (P40 to P47) Port4 is an 8-bit general-purpose Output ports. In addition to functioning as a general-purpose Output port, port4 can also function as an address bus (A0 to A7). Function Setting after reset is released Don’t use this setting Address Bus(A0 to A7) Address Bus(A0 to A7)
Page 69 TMP92CH21 3.5.5 Port 5 (P50 to P57) Port5 is an 8-bit general-purpose Output ports. In addition to functioning as a general-purpose I/O port, port5 can also function as an address bus (A8 to A15). Function Setting after reset is released Don’t use this setting Address Bus(A8 to A15) Address Bus(A8 to A15)
Page 70 TMP92CH21 3.5.6 Port 6 (P60 to P67) Port6 is an 8-bit general-purpose I/O ports. Bits can be individually set as either inputs or outputs by control register P6CR and function register P6FC. In addition to functioning as a general-purpose I/O port, port6 can also function as an address bus (A16 to A23). Function Setting after reset is released Don’t use this setting Address Bus(A16 to A23)
Page 71 TMP92CH21 3.5.7 Port 7 (P70 to P76) Port7 is a 7-bit general-purpose I/O port(P70,P73 and P74 are used for output only). Bits can be individually set as either inputs or outputs by control register P7CR and function register P7FC. In addition to functioning as a general-purpose I/O port, P70 to P76 pins can also function interface-pin for external memory.
Page 72 TMP92CH21 Table 3.5.9 Port7 Registers SYMBOL NAME Address PORT7 001CH In/Out Output In/Out Output P76C P75C P72C P71C PORT7 P7CR 001EH Control Register 0:Input 1:Output P76F P75F P74F P73F P72F P71F P70F PORT7 0:PORT 0:PORT 0:PORT 0:PORT 0:PORT 0:PORT 0:PORT P7FC Function 001FH...
Page 73 TMP92CH21 3.5.8 Port 8 (P80 to P87) Port80 to 87 are 8-bit output ports. Resetting sets output latch of P82 to “0” and output latches of P80 to P81, P83 to P87 to “1”. interface-pin for external memory. Port8 also function as Above setting is used the function register P8FC.
Page 74 TMP92CH21 Port 8 Register bit Symbol (0020H) Read/Write After reset Port 8 Function Register P8FC P87F P86F P85F P84F P83F P82F P81F P80F bit Symbol (0023H) Read/Write After reset 0: PORT 0: PORT Refer Refer 0: PORT 0: PORT 0: PORT 0: PORT Function 1: /CSZE...
Page 75 TMP92CH21 3.5.9 Port9 (P90 to P97) P90 to P94 are 5-bit general-purpose I/O port. I/O can be set on bit basis using the control register. Resetting sets P90 to P94 to input port and all bits of output latch to”1”. P95 is 1-bit general-purpose output port and P96 to P97 are 2-bit general-purpose input port.
Page 76 TMP92CH21 Reset Direction control (on bit basis) P9CR write Function control (on bit basis) P9FC write P91(RXD0,I2SDO) P92(SCLK0,/CTS0,I2SWS) Output latch Selector P9 write I2SDO output SCLK0,I2SWS output Selector P9 read (to PortF1) P91RXD0 in (to PortF2) P92SCLK0 in Figure 3.5.11(2) P91 and P92 (2) P93 (LGOE0), P94(LGOE1), P95(LGOE2) Reset...
Page 77 TMP92CH21 Reset Direction control (on bit basis) P9CR write Funtcion control (on bit basis) P9FC write P95(LGOE2) Output latch Selector P9 write LGOE2 P9 read Figure 3.5.13 Port95 Reset Function control AVCC (on bits basis) TSICR0<PXEN> P-ch <PYEN>...
Page 78 TMP92CH21 Port 9 Register bit Symbol (0024H) Read/Write Input mode After reset Port 9 Control Register P9CR bit Symbol P95C P94C P93C P92C P91C P90C (0026H) Read/Write After reset Function Port 9 Function Register bit Symbol P97F P96F P95F P94F P93F P92F P91F...
Page 79 TMP92CH21 3.5.10 Port A (PA0 to PA7) Port A0 to A7 are 8-bit input ports with pull-up resistor. In addition to functioning as general-purpose I/O ports, port A0 to A7 can also Key-on wake-up function as Keyboard interface. The various functions can each be enabled by writing a “1” to the corresponding bit of the Port A Function Register (PAFC).
Page 80 TMP92CH21 Port A Register bit Symbol (0028H) Read/Write After reset Input Mode Port A Function Register bit Symbol PAFC (002BH) Read/Write After reset 0: KEY IN disable 1: KEY IN enable Port A Control Register bit Symbol PA6C PA5C PA4C PA3C PACR (002AH)
Page 81 TMP92CH21 3.5.11 Port C (PC0 to PC3,PC6 to PC7) PC0 to PC3,PC6 and PC7 are 6-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets Port C to an input port. In addition to functioning as a general-purpose I/O port, Port C can also function as output pin for timers (TA1OUT, TA3OUT and TB0OUT0), input pin for external interruption (INT0 to INT3) , output pin for memory(/CSZF) , output pin for Key(KO8) and output pin for LCD Driver(LDIV,LCP1).
Page 82 TMP92CH21 PC1(INT1,TA3OUT), PC2(INT2,TB0OUT0) , PC3(INT3,TB0OUT1) Reset Direction Control (on bits basis) PCCR write Function control (On bit basis) PCFC write PC1(INT1,TA3OUT) Output latch PC2(INT2,TB0OUT0) Selecter PC3(INT3) PC write TA3OUT TB0OUT0 Selecter PC read INT1 Rising/Falling INT3 edge-detection IIMC<...
Page 83 TMP92CH21 (4) PC7 (/CSZF,LCP1) Reset Direction control (on bit basis) PCCR write Funtcion control (on bit basis) PCFC write Output latch (/CSZF,LCP1) Selector /CSZF PC write LCP1 Selector PC read Figure 3.5.19 Port C7 92CH21 - 79...
Page 84 TMP92CH21 Port C Register bit Symbol (0030H) Read/Write After Reset Input Mode Input Mode Port C Control Register PCCR bit Symbol PC7C PC6C PC3C PC2C PC1C PC0C (0032H) Read/Write After Reset 0: IN 1: OUT 0: IN 1: OUT Port C Function Register bit Symbol PC7F...
Page 85 TMP92CH21 3.5.12 Port F (PF0 to PF2,PF7) Port F0 to F2 are 3-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets PF0 to PF2 to be an input ports. It also sets all bits of the output latch register to “1”.
Page 86 TMP92CH21 Reset Ditection control (On bit basis) PFCR write (RXD0,RXD1) Output latch PF write Selecter PF read PFFC<PF1F> Selecter RXD0 P91RXD0 RXD1 Figure 3.5.22 Port F1 Reset Ditection control (On bit basis) PFCR write (SCLK0,/CTS0, SCLK1,/CTS1) Output latch SCLK0 out Selecter SCLK1 out PF write...
Page 87 TMP92CH21 Reset Funtcion control (on bit basis) PFFC write PF7(SDCLK) Output latch Selector SDCLK PF write PF read Figure 3.5.26 Port F7 92CH21 - 83...
Page 88 TMP92CH21 Port F Register bit Symbol (003CH) Read/Write After Reset Port F Control Register PFCR bit Symbol PF2C PF1C PF0C (003EH) Read/Write After Reset Port F Functon Register bit Symbol PF7F PF2F PF1F PF0F PFFC (003FH) Read/Write After Reset RXD0 pin Selection Function 0: PortF1...
Page 89 TMP92CH21 3.5.13 Port G (PG0 to PG3) PG0 to PG3 are 4-bit input port and can also be used as the analog input pins for the internal AD converter. PG3 can also be used as ADTRG pin for the A/D converter. PG2,PG3 can also be used as MX, MY pin for Touch screen interface.
Page 90 TMP92CH21 3.5.14 Port J (PJ0 to PJ7) PJ0 to PJ4 and PJ7 are 6-bit output port. Resetting sets the output latch PJ to “1”, and they output “1”. PJ5 to PJ6 are 2-bit input/output port. In addition to functioning as port, Port J also functions as output pins for SDRAM (/SDRAS, /SDCAS, /SDWE, SDLLDQM, SDLUDQM, SDULDQM, SDUUDQM and SDCKE) ,SRAM(/SRWR, /SRLLB and /SRLUB) and NANDFlash(NDALE and NDCLE).
Page 91 TMP92CH21 Port J register bit Symbol (004CH) Read/W rite After Reset Port J control register PJCR bit Symbol PJ6C PJ5C (004EH) Read/W rite After Reset Function 0: IN , 1: OUT Port J function register PJFC bit Symbol PJ7F PJ6F PJ5F PJ4F PJ3F...
Page 92 TMP92CH21 3.5.15 Port K (PK0 to PK3) PortK are 4-bit output ports. Resetting sets the output latch PK to “0”, and PK0 to PK3 pins output “0”. In addition to functioning as output ports, PortK also function as output pins for LCD controller (LCP0, LLP, LFR and LBCD).
Page 93: Port
TMP92CH21 3.5.16 Port L (PL0 to PL7) PL0 to PL3 are 4-bit output ports. Resetting sets the output latch PL to “0”, and PL0 to PL3 pins output “0”. PL4 to PL7 are 4-bit general-purpose I/O ports. Each bit can be set individually for input or output using the control register PLCR.
Page 94 TMP92CH21 Port L register bit Symbol (0054H) Read/Write After Reset Port L Control Register PLCR bit Symbol PL7C PL6C PL5C PL4C (0056H) Read/Write After Reset Function 0: IN 1: OUT Port L Function Register PLFC bit Symbol PL7F PL6F PL5F PL4F PL3F PL2F...
Page 95 TMP92CH21 3.5.17 Port M(PM1 to PM2) PM1 to PM2 are 2-bit output ports. Resetting sets the output latch PM to “1”, and PM1 to PM2 pins output “1”. In addition to functioning as ports, PortM also function as output pins for RTC alarm (/ALARM) , output pin for melody/alarm generator (MLDALM, /MLDALM).
Page 96 TMP92CH21 Port M register bit Symbol (0058H) Read/Write After Reset Port M function register PMFC bit Symbol PM2F PM1F (005BH) Read/Write After Reset 0: PORT 0: port Function 1: /ALARM at <PM2>=”1” 1: MLDALM 1: /MLDALM at<PM2>=”0” Port M Drive register PMDR PM2D PM1D...
Page 97: Memory Controller
TMP92CH21 3.6 Memory Controller 3.6.1 Functions TMP92CH21 has a memory controller with a variable 4-block address area that controls as follows. (1) 4-block address area support Specifies a start address and a block size for 4-block address area(block0 to 3). * SRAM or ROM : All CS-blocks(CS0 to CS3) are supported. ...
Page 98 TMP92CH21 Table 3.6(1) Control Register B0CS L Bit s ym b ol B0W W 2 B0W W 1 B0W W 0 B0W R2 B0W R1 B0W R 0 (01 40H ) R ead/W rite After R es et B0CSH Bit S ym b ol B0REC B0O M 1 B0O M 0...
Page 99 TMP92CH21 Table 3.6(2) Control Register Bit S ym b ol BE XO M 1 BE XO M 0 BE XBUS 1 BE XBUS 0 B0CS L BEXC SH (01 40H ) (01 59H ) R ead/W rite After R es et B0CSH Bit S ym b ol BE XW W 2...
Page 100 TMP92CH21 3.6.3 Basic functions and register setting In this section, setting of the block address area, the connecting memory and the number of waits out of the memory controller’s functions are described. (1) Block address area specification The block address area is specified by two registers. The memory start address register(MSARn) sets the start address of the block address areas.
Page 101 TMP92CH21 (iii) Example of register setting To set the block address area 64Kbytes from address 110000H, set the register as follows. MS AR1 R egister bit Sym bol M1S23 M1S22 M1S21 M1S20 M1S19 M1S18 M1S17 M1S16 Specified value M1S23 to 16 bits of the memory start address register MSAR1 correspond with address A23 to A16.
Page 102 TMP92CH21 (2) Connection Memory Specification Setting the BnOM1 to 0 bit of the control register (BnCSH) specifies the memory type to be connected with the block address areas. The interface signal is output according to the set memory as follows BnOM1,BnOM0 bit (BnCSH Regsiter) BnOM1 BnOM0...
Page 103 TMP92CH21 CPU d ata O p erand d ata size O perand start M em ory d ata size C PU address (bit) address (bit) D 31 to D 24 D23 to D1 6 D15 to D8 D 7 to D 0 4n + 0 8/16/32 4n + 0...
Page 104 TMP92CH21 (4) Wait control The external bus cycle completes a wait of two states at least ( 100ns at f =20MHz). Setting the <BnWW2 to 0> and <BnWR2 to 0> of BnCSL specifies the number of waits in the read cycle and the write cycle. BnWW is set with the same method as BnWR. BnWW/BnWR bit (BnCSL Regsiter) BnWW2 BnWW1...
Page 105 TMP92CH21 (5) Recovery(Data-hold) cycle control Some memory have an A.C specification about data-hold time from /CE or /OE for read cycle and a data-confliction problem occurs. To avoid this problem, 1-dummy cycle can be inserted after CSm-block access cycle by setting “1” to BmCSH<BmREC>-register. This 1-dummy cycle is inserted when the next cycle is for another CS-block.
Page 106 TMP92CH21 Basic bus timing (a) External Read / Write Cycle (0 WAIT) SDCLK (20MHz) /CSn A23 to 0 /SRxxB read input D31 to 0 /SRWR write /WRxx D31 to 0 output (b) External Read / Write Cycle (1 WAIT) SDCLK (20MHz) /CSn A23 to 0...
Page 107 TMP92CH21 External Read / Write Cycle (0 WAIT at /WAIT pin input mode) SDCLK (20MHz) /CSn A23 to 0 /SRxxB read D31 to 0 input /SRWR write /WRxx D31 to 0 output /WAIT sampling External Read / Write Cycle (n WAIT at /WAIT pin input mode) SDCLK (20MHz) /CSn...
Page 108 TMP92CH21 Example of WAIT Input Cycle (5WAIT) /WAIT /RES /RES /RES /RES /RES SDCLK /CSn /SRWR SDCLK (20MHz) /CSn FF_RES FF0_D FF0_Q FF1_Q FF2_Q FF3_Q /WAIT 92CH21-104...
Page 109 TMP92CH21 Connecting external memory Figure 3.6.3 shows an example of how to connect external 16bit-SRAM and 16-bit NOR-Flash to the TMP92CH21. TMP92CH21 16bit SRAM /LDS /SRLLB /SRLUB /UDS /SRWR /CS0 I/O[16:1] D[15:0] Not connect ...
Page 110 TMP92CH21 3.6.4 ROM Control (Page Mode) This section describes ROM page mode accessing and how to set registers. ROM page mode is set by the page ROM control register. Operation And How To Set The Resgisters TMP92CH21 supports ROM access of the page mode. The ROM access of the page mode is specified only in the block address area 2.
Page 111 TMP92CH21 3.6.5 Internal Boot-ROM Control This section describes about built-in Boot-ROM. For the specification of S/W in Boot-ROM, refer 3.20 Boot-ROM section. (1) Boot-mode Boot-mode is started by following AM1 and AM0 pins condition with reset. Start mode Don’t use this setting Start with 16-bit data bus Start with 32-bit data bus Start with BOOT(32-bit internal-MROM )
Page 112 TMP92CH21 (4) Disappearing Boot-ROM After Boot-sequence in Boot-mode, an application-system program may continue to run without reset asserting. In this case, an external-memory which is mapped 3FE000H to 3FFFFFH address can not be accessed because of Boot-ROM is assigned. To solve it, internal Boot-ROM can be disappered by setting BROMCR<ROMLESS> to “1”. This <ROMLESS>...
Page 113 TMP92CH21 3.6.6 Cautions (1) Note the timing between /CS and /RD If the parasitic capacitance of the /RD(read signal ) is greater than that of the /CS(Chip Select Signal), it is possible that an uninttended read cycle occurs due to a delay in the read signal. Such an unintended read cycle may cause a trouble as in the case of (a) in Figure 3.6(1).
Page 114 TMP92CH21 (2) Note the NAND-Flash area setting Figure 3.6(3) shows a memory map for NAND-Flash, RAM built-in LCD-driver. And since CS3-area is recommended to assign address from 000000H to 3FFFFFH, this case is explained. In this case, “NAND-Flash, RAM built-in LCD-driver” and CS3-area are overlapped. But each control circuit to access in TMP92CH21 operates independently.
Page 115: 8-Bit Timers (Tmra)
TMP92CH21 3.7 8-bit Timers (TMRA) The TMP92CH21 features 4 built-in 8-bit timers. These timers are paired into four modules: TMRA01 and TMRA23. Each module consists of two channels and can operate in any of the following four operating modes. • 8-Bit Interval Timer Mode •...
Page 116 Prescaler Prescaler TA01RUN Run/Clear clock: φT0 <TA01PRUN> φT1 φT4 φT16 φT256 Timer Timer flip-flop Flip-Flop output: TA1FF TA01RUN<TA0RUN> TA1OUT TA01RUN<TA1RUN> Selector Selector TA1FFCR φT1 φT1 8-Bit Up-Counter 8-bit up counter φT16 φT4 (UC1) (UC0) φT256 φT16 −1 Over flow TA01MOD TA01MOD TA01MOD...
Page 117 Prescaler Prescaler Run/clea TA23RUN clock: φT0 <TA23PRUN> φT1 φT4 φT16 φT256 Timer Timer flip-flop flip-flop output: TA3FF TA3OUT TA23RUN<TA2RUN> TA23RUN<TA3RUN> Selector Selector TA3FFCR φT1 φT1 8-bit Up-Counter 8-bit Comparator φT4 φT16 (UC2) (UC3) φT16 φT256 −1 Over flow TA23MOD TA23MOD TA23MOD <TA2CLK1, TA2CLK 0>...
Page 118 TMP92CH21 3.7.2 Operation of each circuit (1) Prescalers A 9-bit prescaler generates the input clock to TMRA01. The clock φT0 is divided by 4 the CPU clock fsys and input to this prescaler. The prescaler operation can be controlled using TA01RUN<TA0PRUN> in the timer control register.
Page 119 TMP92CH21 (3) Timer registers (TA0REG and TA1REG) These are 8-bit registers, which can be used to set a time interval. When the value set in the timer register TA0REG or TA1REG matches the value in the corresponding up-counter, the Comparator Match Detect signal goes Active. If the value set in the timer register is 00H, the signal goes Active when the up counter overflows.
Page 120 TMP92CH21 (4) Comparator (CP0) The comparator compares the value in an up counter with the value set in a timer register. If they match, the up counter is cleared to zero and an interrupt signal (INTTA0 or INTTA1) is generated. If timer flip-flop inversion is enabled, the timer flip-flop is inverted at the same time.
Page 121 TMP92CH21 3.7.3 SFR TMRA01 Run Register TA01RUN Bit symbol TA0RDE I2TA01 TA1RUN TA0RUN TA01PRUN (1100H) Read/Write After Reset Double IDLE2 Timer Run/Stop control buffer 0: Stop 0: Stop & Clear Function 0: Disable 1: Operate 1: Run (count up) 1: Enable TA0REG double buffer control Timer Run/Stop control Disable...
Page 122 TMP92CH21 TMRA01 Mode Register TA01MOD Bit symbol TA01M1 TA01M0 PWM01 PWM00 TA1CLK1 TA1CLK0 TA0CLK1 TA0CLK0 (1104H) Read/Write After Reset Operation mode PWM cycle Source clock for TMRA1 Source clock for TMRA0 00: 8-Bit Timer Mode 00: reserved 00: TA0TRG 00: (reserved) 01: φT1 01: φT1 01: 16-Bit Timer Mode...
Page 123 TMP92CH21 TMRA23 Mode Register TA23MOD Bit Symbol TA23M1 TA23M0 PWM21 PWM20 TA3CLK1 TA3CLK0 TA2CLK1 TA2CLK0 (110CH) Read/Write After Reset Operation mode PWM cycle TMRA3 clock for TMRA3 TMRA2 clock for TMRA2 00: 8-Bit Timer Mode 00: reserved 00: TA2TRG 00: reserved 01: φT1 01: φT1 01: 16-Bit Timer Mode...
Page 124 TMP92CH21 TMRA1 Flip-Flop Control Register TA1FFCR Bit symbol TAFF1C1 TAFF1C0 TAFF1IE TAFF1IS (1105H) Read/Write After Reset TA1FF 00: Invert TA1FF TA1FF 01: Set TA1FF Control for Inversion Read-Modify 10: Clear TA1FF inversion select -Write Function instructions 11: Don’t care 0: Disable 0: TMRA0 1: Enable 1: TMRA1...
Page 125 TMP92CH21 TMRA3 Flip-Flop Control Register TA3FFCR Bit symbol TAFF3C1 TAFF3C0 TAFF3IE TAFF3IS (110DH) Read/Write After Reset 00: Invert TA3FF TA3FF TA3FF 01: Set TA3FF Control for Inversion Read-Modify 10: Clear TA3FF inversion select -Write Function 11: Don’t care 0: Disable 0: TMRA2 instructions 1: Enable...
Page 126 TMP92CH21 Timer Register Symbol Address TA0REG 1102H undefined TA1REG 1103H undefined TA2REG 110AH undefined TA3REG 110BH undefined Figure 3.7.10 Register for 8-bit Timers 92CH21 - 122...
Page 127 TMP92CH21 3.7.4 Operation in each mode (1) 8-Bit Timer Mode Both timer 0 and timer 1 can be used independently as 8-bit interval timers. Generating interrupts at a fixed interval (using TMRA1) To generate interrupts at constant intervals using timer 1 (INTTA1), first stop TMRA1 then set the operation mode, input clock and a cycle to TA01MOD and TA1REG register, respectively.
Page 128 TMP92CH21 " Generating a 50% duty ratio square wave pulse The state of the timer flip-flop (TA1FF1) is inverted at constant intervals and its status output via the timer output pin (TA1OUT). Example: To output a 2.4-µs square wave pulse from the TA1OUT pin at fsys = 20 MHz, use the following procedure to make the appropriate register settings.
Page 129 TMP92CH21 Making TMRA1 count up on the match signal from the TMRA0 comparator Select 8-Bit Timer Mode and set the comparator output from TMRA0 to be the input clock to TMRA1. Comparator output (TMRA0 match) TMRA0 up-counter (when TA0REG = 5) TMRA1 up-counter (when TA1REG = 2) TMRA1 match output...
Page 130 TMP92CH21 The comparator match signal is output from TMRA0 each time the up-counter UC0 matches TA0REG, though the up-counter UC0 is not be cleared. In the case of the TMRA1 comparator, the match detect signal is output on each comparator pulse on which the values in the up counter UC1 and TA1REG match. When the match detect signal is output simultaneously from both the comparator TMRA0 and TMRA1, the up-counters UC0 and UC1 are cleared to 0 and the interrupt INTTA1 is generated.
Page 131 TMP92CH21 In this mode a programmable square wave is generated by inverting the timer output each time the 8-bit up-counter (UC0) matches the value in one of the timer registers TA0REG or TA1REG. The value set in TA0REG must be smaller than the value set in TA1REG. Although the up counter for TMRA1 (UC1) is not used in this mode, TA01RUN<TA1RUN>...
Page 132 TMP92CH21 Example: To generate 1/4-duty 62.5 kHz pulses (at fsys = 20 MHz): 16 µs Calculate the value which should be set in the timer register. To obtain a frequency of 62.5 kHz, the pulse cycle t should be: t = 1/62.5 kHz = 16 μs φT1 = 0.4 µs (at 20 MHz);...
Page 133 TMP92CH21 (4) 8-Bit PWM Output Mode This mode is only valid for TMRA0. In this mode, a PWM pulse with the maximum resolution of 8 bits can be output. When TMRA0 is used the PWM pulse is output on the TA1OUT pin (which is also used as PC1).
Page 134 TMP92CH21 − 1 In this mode the value of the register buffer will be shifted into TA0REG if 2 overflow is detected when the TA0REG double buffer is enabled. Use of the double buffer facilitates the handling of low duty ratio waves. Match w ith TA0REG Up-counter = Q Up-counter = Q...
Page 135 TMP92CH21 Table 3.7.3 PWM cycle PWM Interval (at fsys = 20MHz) φT1 φT4 φT16 − 1 25.2 µs ( 39.7 kHz ) 100.8 µs ( 9.92 kHz ) 403.2 µs ( 2.48 kHz ) − 1 50.8 µs ( 19.6 kHz ) 203.2 µs ( 4.92 kHz ) 810 µs ( 1.23 kHz ) −...
Page 136 TMP92CH21 3.8. External memory extension function (MMU) This is MMU function which can expand program / data area to 512M byte by having 3 local area. The recommendation address memory map is shown in Fig. 3.8.1 (1), (2). However, when used memory is less than 16M bytes, please refer to section of Memory controller.
Page 137 TMP92CH21 Memory controller setting /ND0CE-pin(128MB) Address Memory map /ND1CE-pin(128MB) 000000H CS0-area Internal I/O,RAM /CS3-pin 32KB COMMON-X 128MB(2MB*64) (2MB) CS3-area 200000H LOCAL-X Bank 0 ・・・ 15 ・・・・・・ (2MB) 400000H LOCAL-Y ・・・ Bank 0 ・・・ 15 (2MB) CS1-area 600000H /SDCS or /C S1-pin COMMON-Y 64MB(2MB*32) (2MB)
Page 138 TMP92CH21 LOCAL-X LOCAL-Y LOCAL-Z 92CH21 /SDCS or /CS1 /CS3,EA24 /CSZA to /CSZF,EA24,EA25 64MB 128MB 64MB*6=384MB /CSZA /CSZD 000000H Bank0 Bank0 Bank0 Bank48 Internal-I/O & RAM /CSZB /CSZE Bank16 Bank64 /CSZC /CSZF Bank32 Bank80 Figure 3.8.1(1) –b Recommendation memory map for maximum specification (Physical) 92CH21-134...
Page 139 TMP92CH21 Memory controller setting /ND0CE-pin(128MB) Address Memory map /ND1CE-pin(128MB) 000000H CS0-area Internal I/O,RAM 32KB COMMON-X (2MB) 200000H LOCAL-X (2MB) Internal Boot-RO M(8KB) 3FE000H 400000H LOCAL-Y (2MB) 600000H COMMON-Y (2MB) 800000H LOCAL-Z Bank 0 ・・・ 15 (4MB) CS2-area C00000H COMMON-Z /SDCS-pin (4MB) 64MB(4MB*16) : Internal Area...
Page 140 TMP92CH21 3.8.2 Control registers There are 12-registers for MMU. They are prepared for 4-purpose using (as Program, data-Read, data-Write and LCDC-display data), and 3-local area(Local-X,Y and Z). By these 4-purpose registers, a data can be accessed easily. (How to use) At first, set enable register and bank-number of each LOCAL register.
Page 141 TMP92CH21 LOCAL-X register for Program LOCALPX bit Symbol (01D0H) Read/Write After reset Use BANK Setting BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.) Function LOCALX 0: not use 1: use LOCAL-Y register for Program LOCALPY bit Symbol (01D1H) Read/Write After reset...
Page 142 TMP92CH21 LOCAL-X register for LCDC-display data LOCALLX bit Symbol (01D4H) Read/Write After reset Use BANK Setting BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.) Function LOCALX 0: not use 1: use LOCAL-Y register for LCDC-display data LOCALLY bit Symbol (01D5H)
Page 143 TMP92CH21 LOCAL-X register for Read data LOCALRX bit Symbol (01D8H) Read/Write After reset Use BANK Setting BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.) Function LOCALX 0: not use 1: use LOCAL-Y register for Read data LOCALRY bit Symbol (01D9H)
Page 144 TMP92CH21 LOCAL-X register for Write data LOCALWX bit Symbol (01DCH) Read/Write After reset Use BANK Setting BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.) Function LOCALX 0: not use 1: use LOCAL-Y register for Write data LOCALWY bit Symbol (01DDH)
Page 145 TMP92CH21 3.8.3 Setting example The below is a setting example. This is in case of using like following condition. Used as Memory Setting MMU-area Logical Physical address address Main NOR-Flash /CSZA, COMMON-Z C00000H to routine (16MB,1pcs) 32bit, FFFFFFH 1wait Character- Bank0 in 800000H to 000000H to...
Page 146 TMP92CH21 (c) Sub routine (Bank-0 in LOCAL-Y) Logical Physical Instruction Comment address address 400000H 400000H 000000H (localwy),81H ; Bank1 in LOCAL-Y is set as Write data for LCD Display RAM 4000xxH 0000xxH (locally), 81H ; Bank1 in LOCAL-Y is set as LCD display data for LCD Display RAM (localrz), 80H ;...
Page 147: Serial Channel
TMP92CH21 3.9 Serial Channels TMP92CH21 includes 2serial I/O channels. For each channels either UART Mode (asynchronous transmission) or I/O Interface Mode (synchronous transmission) can be selected. • I/O Interface Mode Mode 0: For transmitting and receiving I/O data using the synchronizing signal SCLK for extending I/O.
Page 148 TMP92CH21 • Mode 0 (I/O Interface Mode) bit 0 Transfer direction • Mode 1 (7-Bit UART Mode) No parity start bit 0 stop Parity start bit 0 parity stop • Mode 2 (8-Bit UART Mode) No parity start bit 0 stop start parity...
Page 149 TMP92CH21 3.9.1 Block diagrams prescaler φT0 16 32 64 φT2 φT8 φT32 Serial clock generation circuit BR0CR TA0TRG <BR0CK1, 0> (from TMRA0) BR0CR BR0ADD <BR0S3 to <BR0K3 to 0> φ UART φ Mode SIOCLK φ φ BR0CR <BR0ADDE> SC0MOD0 SC0MOD0 <SC1, SC0>...
Page 150 TMP92CH21 prescaler φT0 16 32 64 φT2 φT8 φT32 Serial clock generation circuit BR1CR TA0TRG <BR1CK1, BR1CK0> (from TMRA0) BR1CR BR1ADD <BR1S3 to <BR1K3 to BR1S0> BR1K0> φ UART φ Mode SIOCLK φ φ BR1CR <BR1ADDE> SC1MOD0 SC1MOD0 <SC1, SC0> <SM1, SM0>...
Page 151 TMP92CH21 3.9.2 Operation for each circuit (1) Prescaler, Prescaler clock select There is a 6-bit prescaler for waking serial clock. The prescaler can be run by selecting the baud rate generator as the waking serial clock. Table 3.9.2 shows prescaler clock resolution into the baud rate generator. Table 3.9.2 Prescaler Clock Resolution to Baud Rate Generator System Clock gear...
Page 152 TMP92CH21 (2) Baud rate generator The baud rate generator is a circuit, which generates transmission and receiving clocks that determine the transfer rate of the serial channels. The input clock to the baud rate generator, φT0, φT2, φT8 or φT32, is generated by the 6-bit prescaler which is shared by the timers.
Page 153 TMP92CH21 •Integer divider (N divider) For example, when the source clock frequency (fsys) is 19.6608 MHz, the input clock is φT2 (fsys/16), the frequency divider N (BR0CR<BR0S3 to BR0S0>) = 8, and BR0CR<BR0ADDE> = 0, the baud rate in UART Mode is as follows: fsys/16 ÷...
Page 154 TMP92CH21 Table 3.9.3 Selection of Transfer Rate(1) (when baud rate generator Is used and BR0CR <BR0ADDE> = 0) Unit (kbps) φT0 φT2 φT8 φT32 Input Clock fsys [MHz] (4/fsys) (16/fsys) (64/fsys) (256/fsys) Frequency Divider 18.432000 19.200 4.800 1.200 0.300 19.660800 38.400 9.600 2.400...
Page 155 TMP92CH21 (3) Serial clock generation circuit This circuit generates the basic clock for transmitting and receiving data. •In I/O Interface Mode In SCLK Output Mode with the setting SC0CR<IOC> = 0, the basic clock is generated by dividing the output of the baud rate generator by 2, as described previously.
Page 156 TMP92CH21 (6) The Receiving Buffers To prevent Overrun errors, the Receiving Buffers are arranged in a double-buffer structure. Received data is stored one bit at a time in Receiving Buffer 1 (which is a shift register). When 7 or 8 bits of data have been stored in Receiving Buffer 1, the stored data is transferred to Receiving Buffer 2 (SC0BUF);...
Page 157 TMP92CH21 Handshake function Serial Channels 0, 1 each has a /CTS pin. Use of this pin allows data can be sent in units of one frame; thus, Overrun errors can be avoided. The handshake functions is enabled or disabled by the SC0MOD <CTSE> setting. When the /CTS0 pin foes High on completion of the current data send, data transmission is halted until the /CTS0 pin foes Low again.
Page 158 TMP92CH21 (9) Transmission Buffer The Transmission Buffer (SC0BUF) shifts out and sends the transmission data written from the CPU form the least significant bit (LSB) in order. When all the bits are shifted out, the Transmission Buffer becomes empty and generates an INTTX0 interrupt.
Page 159 TMP92CH21 Parity error <PERR> The parity generated for the data shifted into Receiving Buffer 2 (SC0BUF) is compared with the parity bit received via the RXD pin. If they are not equal, a Parity error is generated. Framing error <FERR> The stop bit for the received data is sampled three times around the center.
Page 160 TMP92CH21 (12) Timing generation # In UART Mode Receiving 8-Bit + Parity Mode 9-Bit 8-Bit, 7-Bit + Parity, 7-Bit (Note) (Note) Interrupt timing Center of last bit Center of last bit Center of stop bit (bit 8) (parity bit) Framing error timing Center of stop bit Center of stop bit Center of stop bit...
Page 161 TMP92CH21 3.9.3 SFR Bit symbol CTSE SC0MOD0 Read/Write (1202H) After Reset Transfer Hand shake Receive Wake up Serial Transmission Serial transmission clock data bit 8 function function Mode (UART) 0: CTS 00: I/O interface Mode 00: TMRA0 trigger disable 0: Receive 0: disable 01: 7-bit UART Mode 01: Baud rate...
Page 162 TMP92CH21 Bit symbol CTSE SC1MOD0 Read/Write (120AH) After Reset Transfer Hand shake Receive Wake up Serial Transmission Serial transmission clock data bit 8 function function Mode (UART) 0: CTS 00: I/O interface Mode 00: TMRA0 trigger disable 0: Receive 0: disable 01: 7-bit UART Mode 01: Baud rate 1: CTS...
Page 163 TMP92CH21 bit Symbol EVEN OERR PERR FERR SCLKS SC0CR Read/Write R(cleared to 0 when read) (1201H) After Reset Received Parity Parity 0: SCLK0 0: baud rate data bit 8 0: odd addition 1: error generator 1: even 0: disable 1: SCLK0 Function 1: enable pin input...
Page 164 TMP92CH21 bit symbol EVEN OERR PERR FERR SCLKS SC1CR Read/Write R (cleared to 0 when) (1209H) After Reset Received Parity Parity 0: SCLK1 0: baud rate data bit 8 0: odd addition generator 1: error 1: even 0: disable 1: SCLK1 pin Function 1: enable input...
Page 165 TMP92CH21 Bit symbol BR0ADDE BR0CK1 BR0CK0 BR0S3 BR0S2 BR0S1 BR0S0 BR0CR Read/Write (1203H) After Reset +(16−K)/16 00: φT0 Always 01: φT2 fixed to “0” division 10: φT8 0: Disable Divided frequency setting Function 11: φT32 1: Enable +(16−K)/16 division enable Setting the input clock of baud rate generator Internal clock φT0 Disable...
Page 166 TMP92CH21 − bit Symbol BR1ADDE BR1CK1 BR1CK0 BR1S3 BR1S2 BR1S1 BR1S0 BR1CR Read/Write (120BH) After reset 00: φT0 (Note) +(16−K)/16 01: φT2 Always division 10: φT8 fixed to “0” 0: Disable Divided Frequency setting Function 1: Enable 11:φT32 Input clock selection for baud rate generator +(16 - K) / 16 division enable Internal clock φT0 Disabled...
Page 167 TMP92CH21 (Transmission) SC0BUF (1200H) (Reveiving) Note: Prohibit read modify write for SC0BUF. Figure 3.9.13 Serial Transmission/Receiving Buffer Registers (channel 0, SC0BUF) Bit symbol I2S0 FDPX0 SC0MOD1 Read/Write (1205H) After Reset IDLE2 duplex Function 0: Stop 0: half 1: Run 1: full Figure 3.9.14 Serial Mode Control Register 1 (channel 0, SC0MOD1) (Transmission)
Page 168 TMP92CH21 3.9.4 Operation in each mode (1) Mode 0 (I/O Interface Mode) This mode allows an increase in the number of I/O pins available for transmitting data to or receiving data from an external shift register. This mode includes the SCLK output mode to output synchronous clock SCLK and SCLK input mode to input external synchronous clock SCLK.
Page 169 TMP92CH21 Transmission In SCLK output mode 8-bit data and a synchronous clock are output on the TXD0 and SCLK0 pins respectively each time the CPU writes the data to the Transmission Buffer. When all data is output, INTES0 <ITX0C> will be set to generate the INTTX0 interrupt. Timing to write transmisison data SCLK0 output...
Page 170 TMP92CH21 " Receiving In SCLK Output Mode the synchronous clock is output on the SCLK0 pin and the data is shifted to Receiving Buffer 1. This is initiated when the Receive Interrupt flag INTES0<IRX0C> is cleared as the received data is read. When 8-bit data is received, the data is transferred to Receiving Buffer 2 (SC0BUF) following the timing shown below and INTES0<IRX0C>...
Page 171 TMP92CH21 Transmission and Receiving (Full Duplex Mode) When Full Duplex Mode is used, set the Receive Interrupt Level to 0 and set enable the level of transmit interrupt. Ensure that the program which transmits the interrupt reads the receiving buffer before setting the next transmit data. The following is an example of this: Example: Channel 0, SCLK output Baud rate = 9600 bps...
Page 172 TMP92CH21 (2) Mode 1 (7-bit UART Mode) 7-Bit UART Mode is selected by setting the Serial Channel Mode Register SC0MOD0<SM1,SM0> field to 01. In this mode a parity bit can be added. Use of a parity bit is enabled or disabled by the setting of the Serial Channel Control Register SC0CR<PE>...
Page 173 TMP92CH21 Main settings 7 6 5 4 3 2 1 0 ← − − − − − − 0 − PFCR Set PF1 to function as the RXD0 pin. – PFFC – – – – – – – 0 SC0MOD0 ← − 0 1 X 1 0 0 1 Enable receiving in 8-Bit UART Mode.
Page 174 TMP92CH21 Protocol Select 9-Bit UART Mode on the master and slave controllers. " Set the SC0MOD0<WU> bit on each slave controller to 1 to enable data receiving. The master controller transmits data one frame at a time. Each frame includes an 8-bit select code which identifies a slave controller.
Page 175 TMP92CH21 Setting example: To link two slave controllers serially with the master controller using the internal clock f as the transfer clock. Master Slave 1 Slave 2 Select code Select code 00000001 00001010 Since Serial Channels 0 and 1 operate in exactly the same way, Channel 0 only is used for the purposes of this explanation.
Page 176 TMP92CH21 3.9.5 Support for IrDA SIO0 includes support for the IrDA 1.0 infrared data communication specification. Figure 3.9.30 shows the block diagram. Transmisison data TXD0 IR modulator IR transmitter & LED IR output SIO0 Modem Receive data RXD0 IR demodulator IR receiver IR input TMP92C820F...
Page 177 TMP92CH21 (3) Data format The data format is fixed as follows: • Data length: 8-bit • Parity bits: none • Stop bits: 1bit (4) SFR Figure 3.9.21 shows the control register SIRCR. Set the data SIRCR during SIO0 is stopping. The following example describes how to set this register: 1) SIO setting ;...
Page 178 TMP92CH21 (5) Notes 1. Baud rate for IrDA When IrDA is operated, set 01 to SC0MOD0<SC1 to 0> to generate baud-rate. The setting except above(TA0TRG, and SCLK0-input) can not be used. 2. The pulse width for transmittion The IrDA 1.0 specification is defined in Table 3.9.2. Table 3.9.2 Baud rate and pulse width specifications Rate Tolerance Pulse Width...
Page 179 TMP92CH21 Table 3.9.3 Baud rate and pulse width for (16 – K) / 16 division function Baud Rate Pulse Width 115.2 kbps 57.6 kbps 38.4 kbps 19.2 kbps 9.6 kbps 2.4 kbps T × 3/16 × (note) T × 1/16 −...
Page 180 TMP92CH21 Bit symbol PLSEL RXSEL TXEN RXEN SIRWD3 SIRWD2 SIRWD1 SIRWD0 SIRCR (1207H) Read/Write After reset Select Receive Transmit Receive Select receive pulse width Set effective pulse width for equal or more than 4x × transmit data 0: disable 0: disable (value + 1) pulse width 0: “H”...
Page 181: Usb Controller
TMP92CH21 3.10 USB Controller 3.10.1 Outline This USB Controller (USBC) is designed for various serial links to construct USB-system. The outline is as follows: (1) Compliant with USB rev1.1 (2) Full-speed (12Mbps) (not supported Low-speed (1.5Mbps)) (3) Auto Bus Enumeration with 384Byte Descriptor-RAM (4) Supported 3 kinds of transfer type: Control, Interrupt and Bulk Endpoint-0: Control 64Bytes*1 -FIFO...
Page 182 TMP92CH21 3.10.1.1 System Configuration The USB Controller (USBC) is consist of following 3-blocks. 1) 900/H1 CPU I/F 2) UDC CORE-block(DPLL,SIE,IFM and PWM), Request Controller, Descriptor-RAM and 4-Endpoint FIFO-RAM 3) USB Tranceiver About above 1) is explained at 3.10.2, and 2) is 3.10.3. Descriptor-RAM 384Byte Request Controller...
Page 183 TMP92CH21 3.10.2 900/H1 CPU I/F The 900/H1 CPU I/F is a bridge between 900/H1-CPU and UDC and it mainly works following operations. ・INTUSB(Interrupt from USB Controller) generation ・A bridge for SFR ・USB clock control (48MHz) 3.10.2.1 SFRs The 900/H1 CPU I/F have following SFRs to control UDC and USB-tranceiver.
Page 184 TMP92CH21 3.10.2.2 USBCR1 register This register is used to set USB-clock enable, tranceiver enable etc. USBCR1 (07F8H) After reset: 00***010B bit symbol TRNS_USE WAKEUP SPEED USB CLKE Write '0' ･TRNS_USE (bit7) 0: Disable internal tranceiver 1: Enable internal tranceiver Set to “1”...
Page 185 TMP92CH21 3.10.2.3 USBINTFRn,MRn register These SFR controls to generate INTUSB(only one interrupt to CPU) because UDC outputs 25 interrupt source. The USBINTMRn are mask registers and the USBINTFRn are flag registers. In the INTUSB routine, execute operations according to generated interrupt source after checking USBINTFRn. The below is the common specification for all MASK and FLAG registers.
Page 186 TMP92CH21 (07F0H) After reset: 0000 00**B USBINTFR1 bit symbol NT_URST_STR N T_URST_END INT_SUS INT_RESUMEINT_CLKSTOP INT_CLKON ･INT_URST_STR (bit7) 0:INT_URST_STR not generated 1:INT_URST_STR generated This is a flag register for INT_URST_STR (USB starting interrupt by USB_RESET ). This is set to “1”...
Page 187 TMP92CH21 (07F1H) After reset: 0000 0000B USBINTFR2 bit symbol EP1_FULL_A EP1_Empty_A EP1_FULL_B EP1_Empty_B EP2_FULL_A EP2_Empty_A EP2_FULL_B EP2_Empty_B USBINTFR3 (07F2H) After reset: 00** ****B bit symbol EP3_FULL_A EP3_Empty_A EPx_FULL_A/B： (When transmitting) This is set to “1”...
Page 188 TMP92CH21 (07F3H) After reset: 0000 000*B USBINTFR4 bit symbol INT_SETUP INT_EP0 INT_STAS INT_STASN INT_EP1N INT_EP2N INT_EP3N ･INT_SETUP (bit7) 0: INT_SETUP not generated 1: INT_SETUP generated This is a flag register for INT_SETUP (USB setup interrupt). This is set to “1”...
Page 189 TMP92CH21 USBINTMR1 (07F4H) After reset: 1111 11**B bit symbol M SK_URST_STSK_URST_EN MSK_SUS MSK_RESUME M SK_CLKSTOP MSK_CLKON ・MSK_URST_STR (bit7) 0：USBINTFR1<INT_URST_STR> is not masked. 1：USBINTFR1<INT_USRT_STR> is masked. This is a mask register for USBINTFR1<INT_URST_STR>. ・MSK_URST_END (bit6) 0：USBINTFR1 <INT_URST_END>...
Page 190 TMP92CH21 (07F5H) After reset: 1111 1111B USBINTMR2 bit symbol EP1_MSK_FA EP1_MSK_EA EP1_MSK_FB EP1_MSK_EB EP2_MSK_FA EP2_MSK_EA EP2_MSK_FB EP2_MSK_EB (07F6H) After reset: 11** ****B USBINTMR3 bit symbol EP3_MSK_FA EP3_MSK_EA EPx_MSK_FA/FB/EA/EB： 1: Each flag resgiter is not masked. ...
Page 191 TMP92CH21 USBINTMR4 (07F7H) After reset: 1111 111*B bit symbol MSK_SETUP MSK_EP0 MSK_STAS MSK_STASN MSK_EP1N MSK_EP2N MSK_EP3N ・MSK_SETUP (bit7) 0：USBINTFR4<INT_SETUP> is not masked. 1：USBINTFR4<INT_SETUP> is masked. This is a mask register for USBINTFR4<INT_SETUP> . ・MSK_EP0 ...
Page 192 TMP92CH21 3.10.3 UDC CORE 3.10.3.1 SFRs The UDC CORE has following SFRs to control UDC and USB-tranceiver. a) FIFO-RAM Endpoint 0-3 FIFO register b) Device request bmRequestType register bRequest register wValue_L register wValue_H register wIndex_L register wIndex_H register wLength_L register wLength_H register c) Status...
Page 193 TMP92CH21 Table3.10.1 UDC CORE SFRs (1/2) Address Read/Write SFR symbol 0500H Descriptor RAM0 0501H Descriptor RAM1 0502H Descriptor RAM2 0503H Descriptor RAM3 067DH Descriptor RAM381 067EH Descriptor RAM382 067FH Descriptor RAM383 0780H ENDPOINT0 0781H ENDPOINT1 0782H ENDPOINT2 0783H ENDPOINT3 0789H EP1_MODE 078AH...
Page 194 TMP92CH21 07D6H INT_Control Table3.10.1 UDC CORE SFRs (2/2) 07D8H StandardRequestMode 07D9H RequestMode 07DEH ID_CONTROL 07DFH ID_STATE 07E0H Port_Status 07E1H FRAME_L 07E2H FRAME_H 07E3H ADDRESS 07E4H Reserved 07E6H USBREADY 07E8H Set Descriptor STALL 92CH21-190 ...
Page 195 TMP92CH21 3.10.3.2 ENDPOINTx register (x:0-3) This register is prepared for each endpoint. This is the window register from or to FIFO-RAM. In the Auto Bus Enumeration, the Request Controller in USBC set mode, which is defined at endpoint descriptor for each endpoint automatically. By this, each endpoint is set to voluntary direction. 1) ENDPOINT0 (0780H) bit symbol EP0_DATA7 EP0_DATA6 EP0_DATA5 EP0_DATA4 EP0_DATA3 EP0_DATA2 EP0_DATA1 EP0_DATA0...
Page 196 TMP92CH21 3.10.3.3 bmRequestType register This register shows the bmRequestType-field of device request. bmRequestType (07C0H) bit symbol DIRECTION REQ_TYPE1 REQ_TYPE0 RECIPIENT4 RECIPIENT3 RECIPIENT2 RECIPIENT1 RECIPIENT0 ・ DIRECTION （ bit7 ） 0 : from Host to Device 1 ： from Device to Host ・...
Page 197 TMP92CH21 3.10.3.5 wValue register There are 2-registers, the wValue_L register shows the lower-byte of wValue -field of device request and wValue_H register shows upper-byte. wValue_H (07C3H) wValue_L ...
Page 198 TMP92CH21 3.10.3.8 Setup Received register This register is used for which an application program tells USBC to recognized INT_SETUP interrupt. Setup Received (07C8H) bit symbol If this register is accessed by an application program, the USBC removes to disabling access to EP0’s FIFO-RAM because the USBC recognized the device request is received.
Page 199 TMP92CH21 3.10.3.10 Standard Request register This register shows the Standard Request which is executing now. A bit which is set to “1” shows current executing request. Standard Request (07CAH) bit symbol S_INTERFACE G_INTERFACE S_CONFIG G_CONFIG G_DESCRIPT S_FEATURE C_FEATURE G_STATUS ...
Page 200 TMP92CH21 3.10.3.12 DATASET register This register shows whether the data exist or not in FIFO-RAM. The application program can check it by accessing this register. In the receiving status, this each bit is set to “1” with generating interrupt after the USBC terminates to receive data from the host, and is reset to “0”...
Page 201 TMP92CH21 3.10.3.13 EPx_STATUS register（x: 0-3） These are status registers for each endpoint. The <SUSPEND> is common for all endpoint. EP0,1,2,3_STATUS (0790H,0791H,0792H,0793H) bit symbol TOGGLE SUSPEND STATUS[2] STATUS[1] STATUS[0] FIFO_DISABLESTAGE_ERR ・TOGGLE Bit (bit6) shows status of toggle sequence bit. ...
Page 202 TMP92CH21 In the other endpoint, the USBC returns to READY after initializing command of The FIFO-RAM. 7：INVALID shows each endpoint is UNCONFIGURED status. In this status, the USBC has no reaction by receiving token from the host. By reset, all endpoint are INVALID status.
Page 203 TMP92CH21 3.10.3.14 EPx_SIZE register（x: 0-3） These registers have following function. a) In the receiving, showing data number for 1-packet which was received correctly. b) In the transmitting, showing payload size. But showing length for the short packet. This register is not needed to read when the USBC is transmitting.
Page 204 TMP92CH21 3.10.3.15 FRAME register This register shows frame-number which is issued with SOF-token from the host and is used for isochronous transfer type. Each H and L-register shows upper and lower bits. whether the data exist or not in FIFO-RAM. FRAME_H (07E2H) －...
Page 205 TMP92CH21 3.10.3.17 EOP register This register is used when a data-phase of control-transfet type is terminating or when a short-packet transmitting of bulk-IN, interrupt-IN. (07CFH) bit symbol EP7_EOPB EP6_EOPB EP5_EOPB EP4_EOPB EP3_EOPB EP2_EOPB EP1_EOPB EP0_EOPB (Note) EOP<EP7_EOPB, EP6_EOPB, EP5_EOPB, EP4_EOPB> registers are not used at TMP92CH21. ...
Page 206 TMP92CH21 3.10.3.18 Port Status register This register is used when a request of printer-class is receiving. In case of request of GET_PORT_STATUS, the USBC operates automatically by using this data. Port Staus (07E0H) bit symbol Reserved7 Reserved6 PaperError Select NotError Reserved2...
Page 207 TMP92CH21 3.10.3.20 Request Mode register This register set answer automatically to class-request in hardware or control in software. Each bit mean kind of request. Each bit mean kind of request. This register is auto-answer at hardware by to reset object bit to ”0”, and it is control in software by to set object bit to “1”. ...
Page 208 TMP92CH21 3.10.3.21 COMMAND register This register set COMMAND at each endpoint. This register can set select of endpoint in bit6-4 and select of kindof COMMAND in bit3-0. It is ignored that outputted COMMAND to don’t support endpoint. COMMAND (07D0H) symbol EP [2]...
Page 209 TMP92CH21 7： FIFO_DISABLE This COMMAND disable FIFO-RAM of applicable endpoint.（EP1-3） If this COMMAND is set from outside, transfer in applicable endpoint send NAK. If this is reciving packet while set from outside, this is valid in next token.
Page 210 TMP92CH21 3.10.3.22 INT_Control register INT_STATUS_NAK-interrupt is disabled and inabled by writing value to this register. This is initialized to disable by outside reset. When received setup-packet,this is disable. INT_Control (07D6H) －－－－－－－ symbol Status_nak －...
Page 211 TMP92CH21 EP1,2,3_MODE (0789H,078AH,078BH) －－ symbol Payload[2] Payload[1] Payload[0] Mode[1] Mode[0] Direction －－ R/Ｗ If you set transaction at SET_CONFIG, SET_INTERFACErequest to software-contorol, after receiced INT_SETUP interrupt, and you must finish weiting to during access to EOP register. This transaction prohibits writing in other timing, and it is ignore.
Page 212 TMP92CH21 3.10.3.25 EPx_SINGLE register This register set mode of FIFO-RAM in each Endpoint. EPx_SINGLE1 (07D1H) symbol EP3_SELECT EP2_SELECT EP1_SELECT EP3_SINGLE EP2_SINGLE EP1_SINGLE (Note) Endpoint3 is only SINGLE-mode at TMP92CH21. Bit 0：No use 1：EP1_SINGLE ...
Page 213 TMP92CH21 3.10.3.27 USBREADY register This register informs USBC on finishing writing data to Descriptor RAM. After store in Descriptor RAM you must write “0” to bit0. USBREADY (07E6H) symbol USBREADY Bit0：USBREADY 0：Finish write to Descriptor RAM. 1：You can write to Descriptor RAM ...
Page 214 TMP92CH21 3.10.3.28 Set Descriptor STALL register This register set Set-Descriptor-request whether returns STALL automatically in data stage or status stage. Set Descriptor STALL (07E8H) symbol S_D_STALL Bit0：S_D_STALL 0：Software contorol （default） 1：Automatically STALL 3.10.3.29 Descriptor RAM ...
Page 215 TMP92CH21 3.10.4 Descriptor RAM This area store Descriptor defined in USB. Device, Config, Interface, Endpoint, String-Descriptor has to set RAM in below Format. Device Descriptor 18byte Config1 ...
Page 216 Device Descriptor 502H BcdUSB(L) USB Spec 1.00 503H BcdUSB(H) ifc's specify own 504H bDeviceClass 505H bDeviceSubClass 506H bDeviceProtocol 507H bMaxPacketSize0 508H BVendor(L) Toshiba 509H BVendor(H) 50AH IdProduct(L) 50BH IdProduct(H) 50CH BcdDevice(L) release 1.00 50DH BcdDevice(H) 50EH bManufacture 50FH iProduct 510H...
Page 217 TMP92CH21 Endpoint1 Descriptor 524H bLength 525H bDescriptorType Endpoint Descriptor 526H bEndpointAddress 527H bmAttributes BULK 528H WMaxPacketSize(L) 64 byte 529H WMaxPacketSize(H) 52AH bInterval Interface0 Descriptor AlternateSetting1 52BH bLength 52CH bDescriptorType Interface Descriptor 52DH bInterfaceNumber 52EH bAlternateSetting AlternateSetting1 52FH bNumEndpoints 530H...
Page 218 TMP92CH21 548H bInterfaceSubClass 549H bInterfaceProtocol 54AH iInterface Endpoint1 Descriptor 54BH bLength 54CH bDescriptorType Endpoint Descriptor 54DH bEndpointAddress 54EH bmAttributes BULK 54FH WMaxPacketSize(L) 64 byte 550H WMaxPacketSize(H) 551H bInterval Endpoint2 Descriptor 552H bLength 553H bDescriptorType Endpoint Descriptor 554H bEndpointAddress 555H bmAttributes BULK 556H...
Page 219 TMP92CH21 56AH bString (Toshiba) 56BH bString 56CH bString 56DH bString 56EH bString 56FH bString 570H bString 571H bString 572H bString 573H bString 574H bString 575H bString 576H bString 577H bString String Descriptor2 String Descriptor3 92CH21-215 ...
Page 220 TMP92CH21 3.10.5 Device Request 3.10.5.1 Standard・Request (1) GET_STATUS Request This request returns automatically status of appointed Reseption side. BmRequestType BRequest wValue wIndex wLength Data 10000000B GET_STATUS Device,Interface or 10000001B Interface Endpoint status 10000010B Endpoint Return below information to according to priority of little-endian in request to Device. Remote SelfPower Wakeup...
Page 221 TMP92CH21 (2) CLEAR_FEATURE Request This request clear Particuler function or disable Particuler function. BmRequestType bRequest wValue wIndex wLength Data CLEAR＿ 00000000B Feature None 00000001B FEATURE Selector Interface 00000010B Endpoint ・Reception side Device FeatureSelector：1 Disable now RemoteWakeup setting. ...
Page 222 TMP92CH21 (4) SET_ADDRESS Request This request is setting DeviceAddress.Following request answer this setting DeviceAddless. Answer on previous Device Address until StatusStage of this request finish normally. BmRequestType bRequest wValue wIndex wLength Data 00000000B SET＿ADDRESS Device Address None (5) GET_DESCRIPTOR request ...
Page 223 TMP92CH21 (6) SET_DESCRIPTOR Request This request set Particuler function or inable Particuler function. BmRequestType BRequest wValue wIndex wLength Data 00000000B SET_ Descriptor Type Descriptor Descriptor DESCRIPTOR Length Descriptor Index Language ID Automatically answer of this request is no support. According to INT_SETUP interrupt, If receiving request discerned SET_DESCRIPTOR request, take back data after EP0_DSET_Abit of DATASET register confirmed “1”.
Page 224 TMP92CH21 (9) GET_INTERFACE Request This request returns Alternate Setting value set appointed interface. BmRequestType bRequest wValue wIndex wLength Data 10000001B GET_ Interface Alternate INTERFACE Setting If there is no appointed interface, it is STALL. (10) SET_INTERFACE Request This request select AlternateSetting in appoint interface. BmRequestType bRequest wValue...
Page 225 TMP92CH21 3.10.5.2 Printer Class Request USBC supports automatically answer about request in Printer class. If it is class except for for printer, you process class request according to INT_SETUP interrupt. This transaction is same Vendor Request. (1) GET_PORT_STATUSRequest ...
Page 226 TMP92CH21 (3) Vendor request （class request） Automatically answers Vendorrequest in USBC don’t support. According to INT_SETUPinterrupt, access to register store of Device Request, and discern receiving request. If this request is Vendor request, massage USBC in outside, and you has to process according to it.
Page 227 TMP92CH21 (b) Contorol Write/Request ・There is no dataphase BmRequestType bRequest wValue wIndex wLength Data 010000xxB Vendorpeculier Vendorpeculier Vendorpeculier None When application receive INT_SETUPinterrupt, Application judge content of Request to bmRequestType, bRequest, wValue, wIndex and wLength register. And you process according to this Request.
Page 228 TMP92CH21 Below is Contorol flow in USBC watch from application. Startup Setting Each EP mode in Set_Config (Interface) Standard request IDLE Printerclass request Enumeration Judge request RD Access to SetupReceived register Contorol-transfer WR Contorol-transfer RD Get_Vendor_Request transaction Set_Vendor_Request transaction...
Page 229 TMP92CH21 3.10.6 Transfer-mode and protocol transaction USBC perform automatically in hardware as follows; Receiveing packet Judgement of address, endpoint and transfer-mode Error process Confirmation of togglebit and CRC in receiving data packet Generation of togglebit and CRC in sending data packet Handshake Answer (1)Protocol outline Below is definition format of USB packet.
Page 230 TMP92CH21 (2) Transfer-mode USBC support transfer-mode in FULL speed. ・FULL speed device contorol-transfer-type Interrupt-transfer-type ...
Page 231 TMP92CH21 (a-1) Sending balk mode Below is transaction・format sending loading balk. It has to follow below. ・Token : IN ・Data : DATA0/DATA1, NAK, STALL ・Handshake : ACK ...
Page 232 TMP92CH21 IDLE Receiveing IN Token Token packet confirmation ・PID ・Address ・Endpoint ・Transfer-mode ・Error INVALID Handshake answer confirmation STALL ・STATUS register(status)confirmation FIFO EMPTY ・DATASET register confirmation DATA PID generation Sending Sending More than MAX ・Attach DATA0 / DATA1 Payload STALL ・DATASIZE register confimation BitStuff Error Set STATUS at STALL...
Page 233 TMP92CH21 (a-2) Receiving balk mode Below is transaction format receiving balk-transfer-type. It has to follow below. ・Token: ・Data: DATA0/DATA1 ・Handshake: ACK,NAK,STALL ...
Page 234 TMP92CH21 IDLE Receving Out Token Token packet Confirmation ・PID ・Address ・Endpoint ・transfer-mode ・Error INVALID Status Confirmation STALL ・Confirming STATUS register(status) FIFO FULL ・Confirmation FIFO’scondition Error transaction ・Set STATUS at RX_ERR Except data PID ・Put back FIFO DATA PID generation Time-out ・DATA0 / DATA1 Addles Point...
Page 235 TMP92CH21 (b) Interrupt-transfer-type Interrupt-transfer-type makes use of transaction-format same sending-balk-transfer. Setting and answer in USBC Hardware transfering Usingtogglebit are same transfering sending balk. It can transfer dosen’t usetogglebit ininterrupt-transfer. In this case, if it receive ACK Handshake to host, renewal toggle-bit, and normally finish.
Page 236 TMP92CH21 (c) Contorol-transfer-type Contorol-transfer-type have below three stages. ・Set-up stage ・Data stage ・Status stage Data stage is skipped sometimes. Each stage has in one or plural transaction. USBC perform each transaction while managing of three stages in Hardware.
Page 237 TMP92CH21 3) Receive Data-packet. Load number of 8byte device-request from SIE in USBC to below request-register. ・bmRequestType register ・bRequest register ・wValue register ・wIndex register ・wLength register 4) After loaded last data, if it doesn’t accord counting CRC compare with loaded CRC, it set STATUS at RX_ERR.And doesn’t return ACK-Hand-shake to host.
Page 238 TMP92CH21 IDLE Receving setup Token Token Packet confirmaition ・PID ・Address ・Endpoint ・transfer-mode ・Error Error transaction ・Set STATUS to RX_ERR INVALID ・Put back FIFO address Status confirmation ・Confirmation STATUS register(status) Except for DATA0 PID DATA PID confirmation ・DATA0 Time-out ・Time-out Error, more than payload data-comunication Receving data...
Page 239 TMP92CH21 (c-2) Data-Stage Data-Stage composed base on togglesequenceby one or plural transaction. Transactionis same format sending or receving balk・transaction. Below is difference. ・toggle bit start from ”1” by SETUP-stage. ・ It judge whether right that IN and OUTToken compare to course-bit of performing Device-Request.
Page 240 TMP92CH21 (c-3-2) OU Status-stage Below is OUTStatus-stage transactionformat. ・Token ： OUT ・Data ： DATA1（0data length）・Handshake ： ACK, NAK, STALL Contorol flow ...
Page 241 TMP92CH21 (c-4)Stage management USBC manage hardware progress of each stage in Contorol-transfer. Receiving Token from SB host or CPU access register performs each stage. Each stage in Contorol-transfer-type has to perform combination software. Below is USBC detecting from 8 byte data in SETUP stage.
Page 242 TMP92CH21 Stage change condition of Contorol・Read-transfer-type ＊Receive SETUPToken from host ・start setup・stage in USBC. ・Receving normally data in request and discern. And assert outside INT_SETUP interrupt. ・Change data・stage into the USBC. ＊Receive INToken from host ・CPU take back request from request-register when it react INT_SETUP interrupt. ・...
Page 243 TMP92CH21 Stage-change conditon of contorol・write- transfer-type ＊Receive SETUPtoken from host. ・Start setup・stage in USBC. ・Receving normally data in request and discern. And assert outside INT_SETUP interrupt. ・Change data・stage into the USBC. ＊Receive OUTToken from host. ・CPU take back request from request-register when it react INT_SETUP interrupt. ・...
Page 244 TMP92CH21 Stage-change conditon of Contorol・write（no datastage）transfer-type ＊Receive SETUPtoken from host ・start setup・stage in USBC. ・receving normally data in request and discern. And assert outside INT_SETUP interrupt. ・Change data・stage into the USBC. ＊Receive INTokenfrom host ・CPU take back request from request-register when it react INT_SETUP interrupt. ・...
Page 245 TMP92CH21 (d) Isochronous-transfer-type Isochronous-transfer-type is guaranteed loading limitted data-number each frame. But it doesn’t retry transfer by differing other three forwrding when error occurs. Therefore isochronous-transfer-type load only 2phaseof token, data and it dosen’t use handshakephase. And dataphase is always DATA0 for this transaction doesn’t support toggle-sequence. Therefore USBC dosen’t confirm when dataPID is receiving mode.
Page 246 TMP92CH21 ・DATASETregister clear packetAbit and it set packetBbit arrangement loading in now frame. ・Set STATUS to READY. USBC finish normally. PacketA’sFIFO can receving nextdata. Interchange packetB’sFIFO in renewed frame and it is loaded in same flow. If don’t receive SOFtoken error and so on, this data is lost by don’t renewal frame.
Page 247 TMP92CH21 IDLE Receiving In Token Tokenpacket confirmation ・PID ・Address ・Endpoint ・transfer-mode ・Error Status confirmation INVALID ・STATUS register(status) confirmation DATA PID generation ・attach DATA0 ・DATASIZE register confirmation Receive SOF Clear Xcondition (A) nothing sending data Set FULL to STATUS Sending data Set LOST to FRAMEregister Error transaction Not renew FRAMEnumber...
Page 248 TMP92CH21 (d-2)isochronousreceiving mode receiving isochronous-transfer-type follow transaction・format in below. ・Token : ・Data DATA0 Contorol flow Isochronous-transfer-type is frame management. And it is taken back CPU in next frame that data writed FIFO in OUT Token. FIFO of isochronousforawrding receving has two conditions below. X.FIFO (FIFO has sending data to host in present frame) （DATASET registerbit＝condition of 0）...
Page 249 TMP92CH21 This renewal stage interchanges part of packetA’s FIFO and packetB’s FIFO. And load same flow. If it receive SOF Token by error and so on, this data loss for renew frame. If nothing problem receiving PID USBC and receving frame-data accompany CRC-error, USBC set LOST to STATUS in FRAME register, don’t renew frame-number.
Page 250 TMP92CH21 IDLE Receiving out Token Token packet confirmation ・PID ・Address ・Endpoint ・transfer-mode ・Error Status confirmation INVALID ・Confirming STATUS register(status) DATA PID confirmation Error, Time-out except for dataPID ・Time-out ・Error Receive SOF Clear Xcondition nothing sending data Receiving data Error, Receiving data more than payload. ・Error ・Receive receiving data Error transaction...
Page 251 TMP92CH21 3.10.7 Businterface and access to FIFO (1) CPUbus・interface USBC prepare two type FIFO-access single packet, dual packet. Single packet mode is using mode implemented FIFOcapacity as big FIFO in hardware. Dual packet mode divides FIFO capacity into two FIFO.
Page 252 TMP92CH21 (a) Single packet mode This is data sequencein single packet mode in using CPUbusI/F. Figure 6.1 is receivingsequence,figure 6.2 is sendingsequence.Main of this chapter is access to FIFO. Datasequencewith USB host show chapter 5. Endpoint 0 can’t change mode by exclusive single packet mode. Shift in single packet and dual packet of Endpoint 1-3 can changing by setting Epx_SINGLE register.
Page 253 TMP92CH21 Below is sending sequencein single packet mode. Wait sending event IDLE Sending event DATASET = 0 DATASET register ・checkbit of EPx_DSET_A DATASET = 1 Distinction Sendingnumber Wait sending rest data Sending number ＞ payload Sending number ＜ payload ・ ...
Page 254 TMP92CH21 (b)Dual-packet-mode Dual-packet-mode is contorol-mode according to priority control in hardware divide FIFO into two independent packets A and B and. It can perform at once sending data and receiveing data to USB host and exchange to outside. When it read out data from FIFO for receiving, you confirm conditon of two packets, and you must to consider the order of priority.
Page 255 TMP92CH21 When you write data to FIFO in sending, you confirm condition of two packets, and you must load after you consider order of loading packetA, B. When you set loading data number, set to which A， Bpacket, you judge by showing PACKET_ACTIVEbit. This packet of Bit0 is loading packet now. You must caution that logic of PACKET_ACTIVEbit in receiving and sending is reverse.
Page 256 TMP92CH21 (c) Issuance of NULLpacket if sending NULLpacket,by input L pulse from EPx_EOPB signal, data of 0rength set to FIFO, and you can sending NULLpacket to INToken. But If set NULLdata to FIFODATA, it valid only SET signal Llevel condition（occasion of don’t have data in FIFO）. ...
Page 257 TMP92CH21 3.10.8 USB device-answer USB controller (USBC) set various register and initialization in USBC in detecting of hardware reset, detecting of USBbusreset, and enumeration answer. Below is explaining about each condition. (1) Condition in detect in busreset. USBC initialize in register detect in busreset on USB signal line and it prepare enumerationmovement from USB host.
Page 258 TMP92CH21 ISO transfer-mode Below is transfer-condition of frame before one. Receiving SOF renews this. OUT(RX) IN(TX) In Initial READY READY Not transfer READY FULL Normally finish DATAIN READY Detect in error RXERR TXERR ...
Page 259 TMP92CH21 7 INVALID This condition mean can’t using endpoint.USBC set INVALID condition to isn’t apointed ENDPOINT, and it ignore all of Token to this endpoint. When initialized it, this conditionoccur always. When USBC detect in hardware reset, it set INVALIDconditionto all endpoint.
Page 260 TMP92CH21 3.10.9 Power management USB contoroller (USBC) can switch from optional resume condition(turn on the power supply condition) to suspend(suspension)condition,and return from suspend condition to turn on the power supply condition. This function can having low electricity consumption by oparating CLK suppling for USBC. (1) Switch to Suspend condition ...
Page 261 TMP92CH21 (4) Low power consumption by contorol of CLK input signal When USBC switch to suspend condition,it stop in CLK and switch to low power consumption condition. But this function enable besides low power consumption by stop to source of CLK supplied to outside as system.
Page 262 TMP92CH21 3.10.10 Supplement (1) Outside access flow to USB communication a) Normally movement setup data0 ack data1 ack in data0 ack data1 ack INT_SETUP INT_ENDPOINT0 INT_STATUS REQUEST FLAG EP0 FIFO access request access SetupReceived access EOP register access b) Stage error ...
Page 263 TMP92CH21 (2) Register beginning value Register name Beginning Beginning Register name Beginning Beginning value value value value Outside reset USB_RESET Outside reset USB_RESET BmRequestType 0x00 0x00 INT_Control 0x00 0x00 Brequest 0x00 0x00 USBBUFF_TEST 0x00 Hold wValue_L 0x00 0x00 USB_STATE 0x01 0x01 wValue_H...
Page 264 TMP92CH21 (3) USB contorol flow chart (a) Transaction to standard request (outline flowchart (exsample)) USBinterrupt Call to USBint0 function Interrupt judgement SETUP ENDPOINT0 STATUS STATUS NAK ENDPOINT１ transaction transaction transaction transaction transaction 92CH21-260 ...
Page 265 TMP92CH21 (b) Condition change Turn on power supply Initialization transaction Normallt finish／No transaction Waiting USB interrupt condition Request error／ Sending STALL Receiving USB Token Transaction error／ Sending STALL Request transaction condition 92CH21-261 ...
Page 266 TMP92CH21 (c) Getting device request and various request judgment START Getting request data Request judgment Standard Request Class Request Vendor Request Error transaction CLEAR_FEATURE ※ Error for ※ Error for SET_FEATURE not support. not support. GET_STATUS SET_ADDRESS SET_CONFIGURATION GET_CONFIGURATION SET_INTERFACE GET_INTERFACE...
Page 267 TMP92CH21 (c-1) Clear Featurerequest transaction START Is request right？ Recipeend judgment DEVICE ENDPOINT Error transaction Disable remote Clear stall setting. wakeup setting. Finish transaction 92CH21-263 ...
Page 268 TMP92CH21 (c-2) Set Featurerequest transaction START Is request right？ Recipeend judgment Error transaction ENDPOINT DEVICE Set stall. Inable remote wakeup setting. Finish transaction 92CH21-264 ...
Page 269 TMP92CH21 (c-3) Get Status-request transaction START Is request right？ Recipeend transacton DEVICE INTERFACE ENDPOINT Error transaction self-power 0x00data Set stall information. supply information. 2byte. Finish transaction 92CH21-265 ...
Page 270 TMP92CH21 (c-4) Set Configration-request transaction START Is request right？ Is EP0 stall？ Is assignment value valid? Is state valid？ Set assignment formation value. Error transaction Clear stall flag Finish transaction 92CH21-266 ...
Page 271 TMP92CH21 (c-5) Get Configration-request transaction START Is request right？ is state valid？ Error transaction Set now formation value Finish transaction 92CH21-267 ...
Page 272 TMP92CH21 (c-6) Set Interface-request transaction START Is request right？ Is Ep0 stall？ Is assignment value valid? Is state valid？ Error transaction Set each endpoint to assignmented formation value. Finish transaction 92CH21-268 ...
Page 273 TMP92CH21 (c-7) Synch Framerequest transaction START Is request right？ Is EP0 stall？ Is assignment value valid？ Is state valid？ Error transaction Set substitute setting value of now sending data. Finish transaction 92CH21-269 ...
Page 274 TMP92CH21 (c-8)Synch Frame-request transaction START Is request right？ Error transaction Finish transaction (c-9) SET DESCRIPTOR-request transaction START Is request right？ Error transaction Error transaction 92CH21-270 ...
Page 275 TMP92CH21 (c-10) Get Descriptorrequest transaction START Is request right？ Is EP0 stall？ Is assignment value valid？ Is state valid？ Error transaction DEVICE CONFIG STRING Set device descriptor Set config ・descriptor Set string・descriptor information. information. information. Write information to FIFO 【ep0_fifowrite( )】...
Page 276 TMP92CH21 (c-11) Data・read transaction to FIFO by EP0 START Is request right？ Stage information=data stage Read data toFIFO STATUS_NAK interrupt STATUS_NAKinterrupt prohibition permission Stage information=stataus stage Data read to FIFO Finish transaction All data number Renew transfer addless 92CH21-272 ...
Page 277 TMP92CH21 (c-12) Data・write transaction to FIFO by EP0 START Is request right？ Set sending size to SIZE register Stage information=data stage Write data to FIFO STATUS_NAKinterrupt permission Is data number decided time of payload size? Set data size to SIZE register STATUS_NAKinterrupt prohibition Write data toFIFO...
Page 278 TMP92CH21 (c-13) Beginning setting transaction of microcontoroller START Interrupt prohibition スタック point setting Various interrupt setting RAM clear UDC initialization【UDC_INIT】 USB farm initialization【USB_INIT】 Interrupt permission Main transaction【main()】 (c-14) Begining setting transaction of USBC START USBC reset transaction 92CH21-274 ...
Page 279 TMP92CH21 (c-15) Beginning transaction of USB farm chaging number START Renewal stage information Renewal カレント information Renewal support information INVALID Ep except EP0 Various flagIntialization (c-16)Set DEVICE_Iddata to DEVICE_ID of UDC. START Set DEVICE_Iddata to DEVICE_ID_RAM area. 92CH21-275 ...
Page 280 TMP92CH21 (c-17)Descriptor dataset transaction START Set descriptor-data to Desc_RAM area. (c-18) USB interrupt transaction START INT registerread Interrupt judgment Others SETUPinterrupt ENPOINT0 interrupt STATUS_NAK interrupt STATUS_interrupt Error 【Proc_ENDPOINT】【Proc_STATUSNAKINT】【Proc_STATUSINT】 transaction transaction 【Proc_SETUPINT】 Request transaction judgment 【status_judge】 92CH21-276 ...
Page 281 TMP92CH21 (c-19) dummy function for not using マスカブル interrupt. ※ T ransaction perform nothing, therefore outline-flow is skip. (c-20) request judgment transaction. If transaction result is error, it put put STALL command. START Is request right？ Error transaction (c-21) SETUPstage transaction START Is request right？...
Page 282 TMP92CH21 (c-22) Perform Endpoint0 transaction in except for SETUPstage. START Stage judgment DATAstage STATUSstage Others Normally finish Error transaction GETsystem request 【ep0_fifowrite】 SETsystem request 【ep0_fiforead】 (c-23)Status・stage interrupt transaction START Status-stage ？ Normally finish Error transaction transaction 92CH21-278 ...
Page 283 TMP92CH21 (c-24) STATUS NAKinterrupt transaction START Data-stage ？ Normally finish Error transaction transaction (c-25)This transaction is no transaction by USB transaction perfprm in interrupts. START 92CH21-279 ...
Page 284 TMP92CH21 (c-26) Getting Descriptor information (reration of standarrd request) START Getting device-information on descriptor Is config within support? Getting config-information on descriptor Interface is within support in config now. Getting device-information on descriptor Increment count to next config-information 92CH21-280 ...
Page 285: Analog/Digital Converter
TMP92CH21 3.11 Analog/Digital Converter The TMP92CH21 incorporates a 10-bit successive approximation-type analog/digital converter (AD converter) with 4-channel analog input. Figure 3.11.1 is a block diagram of the AD converter. The 4-channel analog input pins (AN0∼AN3) are shared with the input-only port Port G so they can be used as an input port. Note: When IDLE2, IDLE1 or STOP Mode is selected, as to reduce the power, with some timings the system may enter a standby mode even though the internal comparator is still enabled.
Page 286 TMP92CH21 3.11.1 Analog/Digital converter registers The AD converter is controlled by the three AD Mode Control Registers: ADMOD0, ADMOD1 and ADMOD2. The five AD Conversion Data Result Registers (ADREG0H/L to ADREG3H/L) store the results of AD conversion. Figure 3.11.2 shows the registers related to the AD converter. AD Mode Control Register 0 −...
Page 287 TMP92CH21 AD Mode Control Register 1 − − − − Bit symbol VREFON I2AD ADCH1 ADCH0 ADMOD1 (12B9H) Read/Write After Reset VREF IDLE2 Note: Note: Note: Note: Analog input channel selection application 0: Stop Always fixed Always fixed Always fixed Always fixed Function control...
Page 288 TMP92CH21 AD Conversion Result Register 0 Low Bit symbol ADR01 ADR00 ADR0RF ADREG0L (12A0H) Read/Write After Reset Undefined Function Stores lower 2 bits of Conversion AD conversion result Data Storage flag 1: Conversion result stored AD Conversion Result Register 0 High Bit symbol ADR09 ADR08...
Page 289 TMP92CH21 AD Conversion Result Register 2 Low Bit symbol ADR21 ADR20 ADR2RF ADREG2L (12A4H) Read/Write After Reset Undefined Stores lower 2 bits of conversion AD conversion result. data storage Function flag 1: Conversion result stored AD Conversion Result Register 2 High Bit symbol ADR29 ADR28...
Page 290 TMP92CH21 3.11.2 Description of operation (1) Analog reference voltage A high-level analog reference voltage is applied to the VREFH pin; a low-level analog reference voltage is applied to the VREFL pin. To perform AD conversion, the reference voltage, the difference between VREFH and VREFL, is divided by 1024 using string resistance.
Page 291 TMP92CH21 (3) Starting AD Conversion To start AD conversion, write a 1 to ADMOD0<ADS> in AD Mode Control Register “0” or ADMOD2<ADTRGE> in A/D Mode Control Register 2, and input falling edge on ADTRG pin. When AD conversion starts, the AD Conversion Busy flag ADMOD0<ADBF> will be set to 1, indicating that AD conversion is in progress.
Page 292 TMP92CH21 ③ Channel Fixed Repeat Conversion Mode Setting ADMOD0<REPET> and ADMOD0<SCAN> to 10 selects Conversion Channel Fixed Repeat Conversion Mode. In this mode data on one specified channel is converted repeatedly. When conversion has been completed, ADMOD0<EOCF> is set to 1 and ADMOD0<ADBF> is not cleared to 0 but held at 1.
Page 293 TMP92CH21 (5) AD conversion time 132state (6.6 µs @ f = 20 MHz) are required for the AD conversion of one channel. (6) Storing and reading the results of AD conversion The AD Conversion Data Upper and Lower Registers (ADREG0H/L to ADREG4H/L) store the results of AD conversion.
Page 294 TMP92CH21 Setting example: ① Convert the analog input voltage on the AN3 pin and write the result, to memory address 2800H using the AD interrupt (INTAD) processing routine. Main routine: 7 6 5 4 3 2 1 0 ← 1 1 0 0 - - - - INTE0AD Enable INTAD and set it to Interrupt Level 4.
Page 295: Watch Dog Timer
TMP92CH21 3.12 Watchdog Timer (Runaway Detection Timer) The TMP92CH21 contains a watchdog timer of runaway detecting. The watchdog timer (WDT) is used to return the CPU to the normal state when it detects that the CPU has started to malfunction (runaway) due to causes such as noise. When the watchdog timer detects a malfunction, it generates a non-maskable interrupt INTWD to notify the CPU of the malfunction.
Page 296 TMP92CH21 The watchdog timer consists of a 22-stage binary counter which uses the clock φ(2/sys) as the input clock. The binary counter can output 2 /fsys, 2 /fsys, 2 /fsys and 2 /fsys. Selecting one of the outputs using WDMOD<WDTP1,WDTP0> generates a watchdog timer interrupt when an overflow occurs.
Page 297 TMP92CH21 3.12.2 Control registers The watchdog timer WDT is controlled by tow control registers WDMOD and WDCR . (1) Watchdog Timer Mode Register (WDMOD) Setting the detection time for the watchdog timer in <WDTP1,WDTP0> This 2-bit register is used for setting the watchdog timer interrupt time used when detecting runaway. On a Reset this register is initialized to WDMOD<WDTP1,WDTP0>...
Page 298 TMP92CH21 − bit symbol WDTE WDTP1 WDTP0 I2WDT RESCR Read/Write WDMOD After reset (1300H) Select detecting time Always IDLE2 1: Internally Always control 00: 2 fixed 0: Stop connects write 0 1: enable “0”. 1: Operate WDT out 01: 2 Function to the 10: 2...
Page 299 TMP92CH21 3.12.3 Operation The watchdog timer generates an INTWD interrupt when the detection time set in the WDMOD<WDTP1,WDTP0> has elapsed. The watchdog timer must be zero-cleared in software before an INTWD interrupt will be generated. If the CPU malfunctions (i.e. if runaway occurs) due to causes such as noise, but does not execute the instruction used to clear the binary counter, the binary counter will overflow and an INTWD interrupt will be generated.
Page 300 TMP92CH21 3.13 Real time clock (RTC) 3.13.1 Function description for RTC 1) Clock function (hour , minute , second) 2) Calendar function (month and day , day of the week , and leap year) 3) 24 or 12-hour (AM/PM) clock function 4) +/- 30 second adjustment function (by software) 5) Alarm function (Alarm output) 6) Alarm interrupt generate...
Page 301 TMP92CH21 3.13.3 Control registers Table 3.13(1) PAGE 0 (Timer function) registers Read/Writ Symbol Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 Bit0 Function SECR 1320h 8 sec. 4 sec. 2 sec. 1 sec. Second column sec. sec. sec. MINR 1321h Minute column 8 min.
Page 302 TMP92CH21 3.13.4 Detailed explanation of control register RTC is not initialized by reset. Therefore, all registers must be initialized at the beginning of the program. (1) Second column register (for PAGE0 only) SECR bit Symbol (1320H) Read/Write After reset Undefined "0"...
Page 303 TMP92CH21 (2) Minute column register (for PAGE0/1) MINR bit Symbol (1321H) Read/Write After reset Undefined "0" is 40 min, 20min, 10min, 8 min. 4 min. 2 min, 1min, Function read. column column column column column column column 0 min. 1 min. 2 min.
Page 304 TMP92CH21 (3) Hour column register (for PAGE0/1) ① In case of 24-hour clock mode (MONTHR<MO0>=’1’) HOURR bit Symbol (1322H) Read/Write After reset Undefined 20 hour 10 hour 8 hour 4 hour 2 hour 1 hour "0" is read. Function column column column column...
Page 305 TMP92CH21 (4) Day of the week column register (for PAGE0/1) DAYR bit Symbol (1323H) Read/Write After reset Undefined Function "0" is read. Sunday Monday Tuesday Wednesday Thursday Friday Saturday (5) Day column register (for PAGE0/1) DATER bit Symbol (1324H) Read/Write After reset Undefined Function...
Page 306 TMP92CH21 (6) Month column register (for PAGE0 only) MONTHR bit Symbol (1325H) Read/Write After reset Undefined Function "0" is read. 10 months 8 months 4 months 2 months 1 month January February March April June July August September October November December (7) Select 24-hour clock or 12-hour clock (for PAGE1 only) MONTHR...
Page 307 TMP92CH21 (8) Year column register (for PAGE0 only) YEARR bit Symbol (1326H) Read/Write After reset Undefined 80 Years 40 Years 20 Years 10 Years Function 8 Years 4 Years 2 Years 1 Year 99 years 00 years 01 year 02 years 03 years 04 years 05 years...
Page 308 TMP92CH21 (10) Setting PAGE register(for PAGE0/1) PAGER bit Symbol INTENA ADJUST ENAALM PAGE (1327H) Read/Write ― After reset Undefined Undefined 1:INT TIMER ALARM PAGE Function enable “0” is read. 1:ADJUST 1:ENABLE 1:ENABLE select (note) 0:DISABLE 0:DISABLE Prohibit Read Modify Write (Note) When INTRTC is used, set following, Select Page0 ld ( pager ), 0ch...
Page 309 TMP92CH21 3.13.5 Operational description (1) Reading timer data ① There is the case, which reads wrong data when carry of the inside counter happens during the operation which timer data reads. Therefore please read two times with the following way for reading correct data.
Page 310 TMP92CH21 ② Readout of timer data that used /ALARM output Timer data can be read with rising edge of /ALARM output by detecting /ALARM='1' with interrupt routine of INTRTC of 1 Hz START RESTR<DIS1HZ>=’0’, RESTR<DIS16HZ>=’1’, PAGER<ENAALM>=’0’ Enable 1Hz output INTRTC? (1Hz) /ALARM=1? (Note)
Page 311 TMP92CH21 (2) Writing timer data When there is carry on the way of write operation, expecting data can not be wrote exactly. Therefore, in order to write in data exactly please follow the below way. ① Resetting a divider In RTC inside, there are 15-stage dividers, which generates 1Hz clock from 32,768KHz.
Page 312 TMP92CH21 ② Disabling the timer Carry of a timer is prohibited when write in '0' at PAGER<ENATMR> and can prevent malfunction by CLOCK HOLD circuit. During a timer prohibited, CLOCK HOLD circuits holds one sec. carry signal, which is generated from divider. After becoming timer enable state, output the carry signal to timer and revise time and continue operation.
Page 313 TMP92CH21 3.13.6 Explanation of the alarm function Can use alarm function by setting of register of PAGE1 and output either of three signal to /ALARM pin as follows. (1) In accordance of alarm register and the timer, output '0'. (2) Output clock of 1Hz. (3) Output clock of 16Hz.
Page 314: Lcd Controller
TMP92CH21 Under Development 3.14 LCD Controller The TMP92CH21 incorporates two types liquid crystal display driving circuit for controlling LCD Driver LSI. One circuit handles a RAM build-in type LCD driver that can store display data in the LCD driver itself, and the other circuit handles a shift-register type LCD driver that must serially transfer the display data to LCD driver for each display picture.
Page 315 TMP92CH21 Under Development 3.14.1 Feature of LCDC of each mode Each feature and operation of pin is as follows. Table 3.14.1 Feature of LCDC of each mode Shift- register type LCD driver control mode RAM built-in type LCD LCDD driver control mode Monochrome, 4, 8, 16 level gray...
Page 316 TMP92CH21 Under Development 3.14.2 SFRs LCDMODE0 Register bit Symbol SCPW1 SCPW0 MODE3 MODE2 MODE1 MODE0 LCDMODE0 RAMTYPE1 RAMTYPE0 (0280H) Read/Write After reset Display RAM LD bus transmission Mode setring speed 0000: Built-in RAM type 0101: STN 8bpp(256) 00: Internal SRAM 00: Reserved 0001: SR 1bpp (mono) 0110: STN 12bpp(4K)
Page 317 TMP92CH21 Under Development LCD Size Setting Register LCDSIZE bit Symbol COM3 COM2 COM1 COM0 SEG3 SEG2 SEG1 SEG0 (0284H) Read/Write After Reset Row setting Column setting 0000 : reserve 0101 : 200 0000 : 0101 : 320 0001 : 0110 : 240 0001 : 0110 : 480...
Page 318 TMP92CH21 Under Development LCDC Source Clock Counter Register LCDSCC bit Symbol SCC7 SCC6 SCC5 SCC4 SCC3 SCC2 SCC1 SCC0 (0287H) Read/Write After Reset Function LCDC Source Clock Counter bit7-0 LCD Clock Counter Register0 LCDCCR0 bit Symbol PCPV2 PCPV1 PCPV0 (0288H) Read/Write...
Page 319 TMP92CH21 Under Development LCD RED Palette Register LCDRP10 bit Symbol (0291H) Read/Write After Reset 256 color STN mode 256 color STN mode Function RED1 level setting RED0 level setting LCDRP32 bit Symbol (0292H) Read/Write After Reset 256 color STN mode 256 color STN mode Function RED3 level setting...
Page 320 TMP92CH21 Under Development LCD GREEN Palette Register LCDGP10 bit Symbol (0295H) Read/Write After Reset 256 color STN mode 256 color STN mode Function GREEN1 level setting GREEN0 level setting LCDGP32 bit Symbol (0296H) Read/Write After Reset 256 color STN mode 256 color STN mode Function GREEN3 level setting...
Page 321 TMP92CH21 Under Development LCD OE0 control Register LCDOE00 bit Symbol OE007 OE006 OE005 OE004 OE003 OE002 OE001 OE000 (02B0H) Read/Write After Reset Function OE0 CONTROL OF GATE DRIVER OF TFT PANEL LCDOE01 (02B1H) LCDOE04 (02B4H) LCDOE05 (02B5H) bit Symbol OE057 OE056 OE055...
Page 322 TMP92CH21 Under Development Start address register ROW number setting register ----- (bit23-16) (bit15-8) (bit7-1) (bit8) (bit7-0) LSARAH LSARAM LSARAL CMNAH CMNAL ----- A-area (02A2H) (02A1H) (02A0H) (02A4H) (02A3H) LSARBH LSARBM LSARBL CMNBH CMNBL ----- B-area (02A8H) (02A7H) (02A6H) (02AAH) (02A9H) LSARCH...
Page 323 TMP92CH21 Under Development 3.14.3 Shift-register type LCD driver control mode (SR mode, STN color) 3.14.3.1 Description of operation Set the mode of operation, start address of source data save memory, gray-scale level and LCD size to control registers before setting start register. After set start register LCDC outputs bus release request to CPU and read data from source memory.
Page 324 TMP92CH21 Under Development 3.14.3.2 Memory Space (Common spec. SR and TFT mode) The LCDC can display the LCD panel image which is divided horizontally into 3 parts; upper, middle and lower. Each area calls A, B and C area that has some characteristics showing below.
Page 325 TMP92CH21 Under Development 3.14.3.3 Display memory mapping and Panning Function (Common spec. SR and TFT) LCDC can change the panel window if only you change each start address of A, B and C area. Display area can be vertical and horizontal panned by changing row and column address.
Page 326 TMP92CH21 Under Development Relation of Memory map image and Output data Monochrome (1 bpp (bit per pixel)) Display memory image Address 0 Address 1 Address 2 Address 3 MSB 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 LD bus output sequence 4bitA type 4bitB type...
Page 327 TMP92CH21 Under Development Relation of Memory map image and Output data 8/16Gray (4 bpp: 8gray case, valid data is 3bit but data space need to 4bit) Display memory image Address 0 Address 1 Address 2 Address 3 MSB ...
Page 328 TMP92CH21 Under Development Relation of Memory map image and Output data 256 Color (8 bpp; R:3bit,G:3bit,B:2bit) Display memory image Address 0 Address 1 Address 2 Address 3 MSB 4 5 6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Address 4 Address 5 Address 6...
Page 329 TMP92CH21 Under Development Relation of Memory map image and Output data 4096 Color (12 bpp: R:4bit, G:4bit, B:4bit) Display memory image Address 0 Address 1 Address 2 Address 3 MSB 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R1 ...
Page 330 TMP92CH21 Under Development 3.14.3.5 Refresh rate setting Frame cycle (refresh rate) is generated from setting of LSCC and FFP. LBCD terminal out one pulse every this cycle and LFR normally out invert signal every this cycle. But when DEVIDE FRAME function is used, LFR signal change to special signal for high quality display.
Page 331 TMP92CH21 Under Development (2) Refresh rate adjust function (correct function) In this function, LBCD frequency: refresh rate is generated by setting by LCDSCC<SCC[7:0]> and FFP<FP[9:0]> register. FFP value is normally set same value of ROW number, but this value can use for correction of BCD frequency: refresh rate.
Page 332 TMP92CH21 Under Development (3) Divide frame adjust function We call divide frame adjust function that can available to decrease uneven display in big size LCD panel. When this function is enabled by set to <FRMON>=1, LFR signal change out level high and low, every product of LLP cycle and setting value in follows LCDDVM register.
Page 333 TMP92CH21 Under Development =78.02Hz (@<FP8:0>=120) 1-picture display time LBCD LD7-LD0 (8bit case) Use internal signal Data transmission to CPU(interrupt) (1row data) Whole timing diagram of SR mode t LP: LLP cycle LBCD t OPR:CPU opration time t STOP: stop time Use internal signal tLPH=0.5XT tCP=2state...
Page 334 TMP92CH21 Under Development 3.14.3.6 LCD data transmission speed and data bus occupation rate After set start register LCDC outputs bus release request to CPU and read data from source memory. After that LCDC transmits data of volume of LCD size to external LCD driver through special LCDC data bus (LD11-LD0).
Page 335 TMP92CH21 Under Development 3.14.3.7 Timing Diagram of LD bus TMP92CH21 can select to display RAM for external SRAM: available to set WAIT, internal SRAM and external SDRAM: 16, 32, 64, 128, 256 and 512Mbit. And as 480Bytt FIFO buffer is built in this LCDC, LD bus speed can control. That speed can select in 3 kind of cycle: (fsys/2, fsys/4, fsys/8) LD bus data:LD11 to LD0 is out at rising edge of LCP0, LCDD receive at falling edge of LCP0.
Page 336 TMP92CH21 Under Development Internal system clock (fSYS) A23 to A0 IN+4 IN+5 D32 to D0 or D15 to D0 IN+1 IN+2 IN+3 8bit bus 32bit bus width, monochrome /4Gray/256 color OUT+1 OUT+1 OUT+2 OUT+2 OUT+3 OUT+3 OUT+4 OUT+4 LD7 to LD0 16bit bus width, monochrome /4Gray/256 color...
Page 337 TMP92CH21 Under Development fs ys Colu mn A 2 3 to A 0 R o w /R D D 3 1 to D 0 o r D 1 6 to D 0 IN +1 IN +2 IN +3 IN +4 IN +5 IN +6...
Page 338 TMP92CH21 Under Development 3.14.3.8 Setting of color palette TMP92CH21 can support monochrome, 4,8,16 level gray scale, color STN panels, and color TFT panels. It shows as follows how to set each mode. Monochrome No need to special setting, it’s just select monochrome mode by LCDMODE1<MODE[3:0]> register.
Page 339 TMP92CH21 Under Development STN4096 color It just select STN4096 mode by LCDMODE1<MODE[3:0]>. This LCDC is 4096 color palette maximum. If select STN4096 color mode, it can’t adjust each color contrast level. 92CH21-335...
Page 340 TMP92CH21 Under Development 3.14.3.9 Example to connect SR type LCDD COM 001 240CO M × × × × 80SEG LCD (Color) COM 240 T 6C13B 92CH21 (240-row driver selection) V DD O001 COM 001 TES T 240CO M × × × × 240SEG Di7-Di0 DUA L LCD(M onochrom e)
Page 341 TMP92CH21 Under Development 3.14.3.10 Program example (4K color STN) ;******** PORT settings ********* (plfc),0ffh ; LD7-LD0 set (plcr),0f0h ; output mode (pkfc),0fh ; LBCD,LLP,LCP0) ;******** LCD settings ********* (LCDSCC),31 ; counter for LP (Refresh Rate:220Hz＠27MHz) (LCDCCR0),01h ; (LCDCCR1),01h ; SCP Negedge (LCDCCR2),02h ;...
Page 342 TMP92CH21 Under Development 3.14.4 TFT color display mode 3.14.4.1 Description of operation It is basically same setting to SR mode. Set the mode of operation, start address of source data save memory, color level and LCD size to control registers before setting start register. After set start register, LCDC outputs bus release request to CPU and read data from source memory.
Page 343 TMP92CH21 Under Development Relation of Memory map image and Output data 256 Color (8 bpp; R:3bit,G:3bit,B:2bit) Display memory image Address 0 Address 1 Address 2 Address 3 MSB 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Address 4 Address 5 Address 6...
Page 344 TMP92CH21 Under Development Relation of Memory map image and Output data 4096 Color (12 bpp; R:4bit,G:4bit,B:4bit) Display memory image Address 0 Address 1 Address 2 Address 3 MSB 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Address 4 Address 5 Address 6...
Page 345 TMP92CH21 Under Development 3.14.4.5 Setting each control signals TFT source driver is controlled by LCP1:base clock (LCP0), data start clock (LFR) and load pulse (LLP). Special data bus: LD11 to 0 is used 8bit of 12bit for suitable LCDD. Each signal can seriously adjust timing using some control register.
Page 346 TMP92CH21 Under Development LCD Clock Counter Register0 LCDCCR0 bit Symbol PCPV2 PCPV1 PCPV0 (0288H) Read/Write After Reset Pre LCP1 CLK: Function Dummy clock number to valid clock of LCP1 LCD Clock Counter Register1 LCDCCR1 bit Symbol TLDE4 TLDE2 TLDE1 TLDE0 TLDE3...
Page 347 TMP92CH21 Under Development 3.14.5 Source driver control Detail timing is below LCP1 counter GN (Gate Number) LCP1 (rise up setting) LLP setting offset High level width of LLP 16SYSCLK Column number ...
Page 348 TMP92CH21 Under Development 3.14.5.1 Gate driver control TFT gate driver is controlled by LCP1:base clock and LBCD: vertical shift data signal. TMP92CH21 has LGOE2 to LGOE0:3bit output enable signals and these LGOE2 to LGOE0 can available to control individually. TFT gate driver’s output can be controlled by this serious timing and can available to make blanking adjustment and to zoom function.
Page 349 TMP92CH21 Under Development TMP92CH21 has LGOE2 to LGOE0 pins to control 3kind of gate output individually. LGOE0 start to out from rising up timing of LCP1’s 1’st pulse and repeat out each 3 pulse of LCP1. LGOE1 start to out from LCP1’s 2’nd pulse, LGOE2 start to out from LCP1’s 3’rd pulse.
Page 350 TMP92CH21 Under Development 3.14.5.2 Example to connect TFT LCDD JB T 6L78-AS (162-gate d riv er) 92C H 2 1 VD D VD D U /D T EST 1 T EST 2 160S EG × × × × 3(R G B )× × × × 162C O M LC D LG O E2 -0 O E3-1...
Page 351 TMP92CH21 Under Development 3.14.6 Built-in RAM type LCDD mode 3.14.6.1 Description of operation Data transmission to LCD driver is executed by move instruction of CPU. After setting mode of operation to control register, when move instruction of CPU is executed LCDC outputs chip select signal to LCD driver connected to the outside from control pin (LCP0 etc.).
Page 352 TMP92CH21 Under Development 3.14.6.3 Sequential access type Data transmission to LCD driver is executed by move instruction of CPU. After setting mode of operation to control register, when move instruction of CPU is executed LCDC outputs chip select signal to LCD driver connected to the outside from control pin (LCP0 etc.).
Page 353 TMP92CH21 Under Development 3.14.6.4 Example to connect built-in RAM LCDD T 6B66A 92CH21 (65-row driver) V DD COM 001 COM 001 65CO M × × × × 80SEG VLC1,VLC2, VLC3,VLC4, VLC5 COM 065 COM065 LCP0 /W R /W R /DOFF /DSP OF DB 0〜...
Page 354 TMP92CH21 Under Development 3.14.6.5 Example for programming Setting example : In case of use 80SEG X 65COM LCD driver. Assign external column driver to LCDC1 and row driver to LCDC4. This example used LD instruction in setting of instruction and used burst function of micro DMA by soft start in setting of display data.
Page 355: Melody / Alarm Generator
TMP92CH21 3.15 Melody / Alarm generator(MLD) TMP92CH21 contains melody function and alarm function, both of which are output from the MLDALM pin. Five kind of fixed cycles INTERRUPT is generate by using 15bit counter, which is used for alarm generator. Features are as follows.
Page 356 TMP92CH21 3.15.1 Block Diagram Internal Data Bus Reset [Melody Generator] MELFH,MELFLResistor MELFH <MELON> MELOUT invert Comparator(CP0) Stop&clear clear Low-speed 12bit counter(UC0) clock INTALM0(8KHz) INTALM1(512Hz) INTALM2(64Hz) INTALM3(2Hz) INTALM4(1Hz) 15bit counter(UC1) INTALMH ALMINT <IALM4E:0E> (HALT release) 4096Hz MELOUT MELALMC<AC[1:0]> 8bit counter(UC2) selector MLDALM pin invert Alarm wave form...
Page 357 TMP92CH21 3.15.2 Control registers ALM register bit Symbol (1330H) Read/Write After reset Function Setting alarm pattern MLDALMC register MELALMC bit Symbol ALMINV MELALM (1331H) Read/Write After reset Free-run counter control Output Alarm 00: Hold Waveform Wavefor Write “0” select 01: Restart Function m invert 0: Alarm...
Page 358 TMP92CH21 3.15.3 Operational Description 3.15.3.1 Melody generator The Melody function generates signals of any frequency (4Hz- 5461Hz) based on low-speed clock (32.768KHz) and outputs the signals from the MLDALM pin. By connecting a loud speaker outside, Melody tone can easily sound. (Operation) At first, MELALMC<MELALM>...
Page 359 TMP92CH21 3.15.3.2 Alarm generator The Alarm function generates eight kinds of alarm waveform having a modulation frequency 4096Hz determined by the low-speed clock (32.768KHz). And this waveform is reversible by setting a value to a register. By connecting a loud speaker outside, Alarm tone can easily sound. Five kind of fixed cycles (1Hz, 2Hz, 64Hz, 512Hz, 8KHz) INTERRUPT be generate by using a counter which is used for alarm generator.
Page 360 TMP92CH21 Example: Waveform of alarm pattern for each setting value: not invert) AL1 pattern Modulation frequency(4096Hz) (Continuous output) AL2 pattern (8 times/1sec) 31.25ms 1sec AL3 pattern 500ms (once) AL4 pattern (Twice/1sec) 62.5ms 1sec AL5 pattern (3 times/1sec) 1sec 62.5ms AL6 pattern (once) 62.5ms AL7 pattern...
Page 361: Sdram Controller
TMP92CH21 3.16 SDRAM Controller (SDRAMC) TMP92CH21 includes SDRAM controller which supports SDRAM access by CPU/LCDC. The features are as follows. (1) Support SDRAM ・Data Rate Type : Only SDR(Single Data Rate) Type ・Bulk of Memory : 16 / 64 / 128 / 256 / 512Mbit ・Number of Bank : 2 / 4 Banks ・Width of Data Bus...
Page 362 TMP92CH21 3.16.1 Control Registers Figure 3.16.1(1) shows the SDRAMC control registers. Setting these registers controls the operation of SDRAMC. SDRAM Access Control Register 1 SDACR1 Bit symbol SASFR SMRD SWRC SBST SWMOD SRBL SMAC (0250H) Read/Write After Reset Selecting Mode Write Burst Selecting...
Page 363 TMP92CH21 SDRAM CoMMand register SDCMM Bit symbol SCMM2 SCMM1 SCMM0 (0253H) Read/Write After Reset Issuing Command (note2) (note3) 000: Not Issue 001: Initialize Sequence a. Precharge All Banks Function b. 8 Times Auto Refresh c. Mode Register Set 100: Mode Register Set 101: Self Refresh Entry 110: Self Refresh Exit other: Reserved...
Page 364 TMP92CH21 3.16.2 Operation description (1) Memory access control SDRAM controller is enabled when SDACR1<SMAC>=1. And then SDRAM control Signals (SDCS, SDRAS, SDCAS, SDWE, SDLLDQM, SDLUDQM, SDULDQM, SDUUDQM, SDCLK and SDCKE) are outputted during the time CPU or LCDC accesses CS1 or CS2 area. In the access cycle, Address multiplex outputs row/column address through A0 to A15 pin.
Page 365 TMP92CH21 85 state (320Byte read) SDCLK SDCKE SDUUDQM SDULDQM SDLUDQM SDLLDQM SDCS SDRAS SDCAS SDWE A15-A0 …… CA(n CA(n+4) CA(n+8 CA(n+12 (n+312 (n+316 D31-0 …… D(n+4 D(n+8 D(n+12 D(n+312 D(n+316 Bank All bank Active Precharge Figure 3.16.2(1) Timing of burst read cycle ...
Page 366 TMP92CH21 (3) Refresh Control TMP92CH21 supports two Refresh commands of Auto-Refresh and Self-Refresh. (a) Auto-Refresh The Auto-Refresh command is automatically generated at intervals set by SDRCR<SRS0-2> by making it to SDRCR<SRFC> to "1". The generation interval can be set between 47-312states (2.4us-15.6us at fsys=20MHz).
Page 367 TMP92CH21 (b) Self-Refresh The Self-Refresh command is generated by making it to SDCMM<SCMM0 to SCMM2> to "101". The Self-Refresh cycle is shown in Fig. 3.16.2(4). During Self-Refresh, Refresh is performed inside SDRAM (an Auto-refresh command is not needed). The Auto-Refresh command is automatically executed once when Self-Refresh is released, and Refresh is done according to the setting of the Auto-Refresh command after that.
Page 368 TMP92CH21 (4) SDRAM Initialize TMP92CH21 can generate the following SDRAM initialize routine after injection power-supply to SDRAM. The cycle is shown in Fig. 3.16.2 (5). 1. Pre-charge of all banks 2. The auto-refresh cycle of 8 cycles 3. The initial configuration to a mode register The above cycle is generated by setting SDCMM<SCMM0 to SCMM2>...
Page 369 TMP92CH21 (5) Connection Example The example of connection with SDRAM is shown in table 3.16.2(3) and figure 3.16.2. (9). Table 3.16.2(4) Connection with SDRAM SDRAM Pin Name 92CH21 Data bus width 16bit Data bus width 32bit Pin Name 128M 128M 128M 256M 512M...
Page 370 TMP92CH21 Fig. 3.16.2 (7) Connection with SDRAM(1MWord×16bit×2) TMP92CH21 SDCLK SDCKE A11-A0 A11-A0 D15-D0 D15-D0 D31-D16 SDRAS SDCAS SDWE SDCS SDLUDQM UDQM SDLLDQM LDQM SDUUDQM SDULDQM A11-A0 D15-D0 UDQM LDQM Fig. 3.16.2 (8) Connection with SDRAM(512KWord×32bit) TMP92CH21 SDCLK SDCKE A10-A0 A10-A0 D31-D0...
Page 371: Nand-Flash Controller
TMP92CH21 3.17 NAND Flash Controller 3.17.1 Characteristics The NAND Flash Controller (NDFC) generates the control signals required to interface with the NAND Flash. It has also the ECC calculating circuits. This product has 2-v. External pins except Chip-Enable are multiplexed . They are selected by NDCR<CHSEL>...
Page 372 TMP92CH21 3.17.2 Block Diagram NAND Flash Controller Channel-0 (NDFC0) G-Bus G-Bus I/F Registers ND CE* /ND0CE Register ND ALE Address NDCLE, ND CLE NDALE, NAND ND_RE* /NDRE, Host I/F timing Flash I/F /NDWE, Control Timing ND WE* D7 to D0 Control ND RB* DATA_OUT[7:0]...
Page 373 TMP92CH21 3.17.3 Detailed Explanation 3.17.3.1 Access to NAND Flash The NDFC supports the interface between the NAND Flash using register indirect sequence. It has the ECC calculating circuits. Please see 3.17.3.2 in detail of the ECC. This section describes the procedure to access to NAND Flash. Basically, set the command in ND0FMCR at first and then read or write in ND0FDTR.
Page 374 TMP92CH21 (5) Write 16 bytes redundant data • ND0FMCR :Set 0x90 to do the data mode without ECC. • ND0FDTR :Write 16 bytes redundant data. D520: LPR[23:16] D521: LPR[31:24] D522: CPR[11:6], 2’b11 D525: LPR[7:0] D526: LPR[15:8] D527: CPR[5:0], 2’b11 (6) Run Page Program •...
Page 375 TMP92CH21 3) Read The read sequence is below. (1) ND0FMCR :Set 0x70 to reset ECC data. (2) Read 512 bytes • ND0FMCR :Set 0x11 to assert NDCLE signal and do the command mode. • ND0FDTR :Set 0x00 to write the Read command. •...
Page 376 TMP92CH21 4) ID Read The ID read sequence is below. (1) ND0FMCR :Set 0x11 to assert NDCLE signal and do the command mode. (2) ND0FDTR :Set 0x90 to write the ID Read command. (3) ND0FMCR :Set 0x12 to assert NDALE signal and do the address mode. (4) ND0FDTR :Set 0x00.
Page 377 TMP92CH21 3.17.4 Registers Table 3.17.4(1)-a NAND Flash Control Registers for Channel-0 Address Register Register Name 1D00H ND0FDTR NAND Flash Data transfer Register (1D00H-1EFFH) 1CB0H ND0ECCRD NAND Flash ECC-code read Register (1CB0H-1CB5H) 1CC4H ND0FMCR NAND Flash Mode Control Register 1CC8H ND0FSR NAND Flash Status Register 1CCCH ND0FISR...
Page 378 TMP92CH21 3.17.4.1 NAND Flash Data Transfer Register (ND0FDTR, ND1FDTR) DATA : Type  : Default Bit(s) Mnemonic Field Name Description 7 : 0 DATA DATA NAND Flash data. Read: Be able to read the data that was read from the NAND Flash. Write: The data is written to the NAND Flash.
Page 379 TMP92CH21 3.17.4.2 NAND Flash ECC-code Read Register (ND0ECCRD, ND1ECCRD) ECC-code : Type  : Default Bit(s) Mnemonic Field Name Description 7 : 0 ECC-code ECC-code NAND Flash calculated ECC data. (Note1) Both ND0ECCRD and ND1ECCRD are assigned to same address. It depend on NDCR<CHSEL> register whether which channel is accessed.
Page 380 TMP92CH21 3.17.4.3 NAND Flash Mode Control Register (ND0FMCR, ND1FMCR) ECC1 ECC0 PCNT1 PCNT0 ALE R/W : Type : Default Bits Mnemonic Field Name Description Write Enable (Default: 0) Write Enable This bit enables the data write operation. When you write the data to the NAND flash, this bit must be set one.
Page 381 TMP92CH21 3.17.4.4 NAND Flash Status Register (ND0FSR, ND1FSR) BUSY : Type  : Default Mnemonic Field Name Description BUSY (Default: Undefined) BUSY BUSY This bit shows the status of NAND flash. 0: Ready 1: Busy   6 : 0 Reserved (Note1) Since a noise-filter for some-states are built-in the NDFC, when NDR/B-pin changes, a <BUSY>-flag don’t change at the same time.
Page 382 TMP92CH21 3.17.4.5 NAND Flash Interrupt Status Register (ND0FISR, ND1FISR) : Type : Default Mnemonic Field Name Description   7 : 1 Reserved Ready Ready (Default: 0) This bit is set when NDR/B signal changes from Low(means BUSY) to High(means READY) if NDFIMR<MRDY>...
Page 383 TMP92CH21 3.17.4.7 NAND Flash Strobe Pulse Width Register (ND0FSPR, ND1FSPR) : Type 0000 : Default Mnemonic Field Name Description   7 : 4 Reserved 3 : 0 Strobe Pulse Strobe Pulse Width (Default: 0000) Width These bits specify the Low pulse width of the /NDRE and /NDWE signals. The low pulse width is the value of this field plus one f clock.
Page 384 TMP92CH21 3.17.4.8 NAND Flash Reset Register (ND0FRSTR ,ND1FRSTR) : Type : Default Mnemonic Field Name Description   7 : 1 Reserved Reset Reset (Default: 0) Setting this bit reset the NDFC(except NDCR<CHSEL> register). After reset, this bit is cleared automatically. 0: Don’t care 1: Reset (Note1) After writing <RST>...
Page 385 TMP92CH21 3.17.5 Timing Diagrams 3.17.5.1 Command and Address Cycle ND0FMCR<ALE> = 0 ND0FMCR<CLE> = 0 ND0FMCR<ALE> = 1 ND0FMCR<CLE> = 1 ND0FMCR<CE> = 1 Figure 3.17.5(1) Command and Address Cycle 92CH21-381...
Page 386 TMP92CH21 3.17.5.2 Data Read Cycle Figure 3.17.5(2) Data Read Cycle (ND0FSPR = 0x02) 92CH21-382...
Page 387 TMP92CH21 3.17.5.3 Data Write Cycle Figure 3.17.5(4) Data Write Cycle (ND0FSPR = 0x03) 92CH21-383...
Page 388 TMP92CH21 3.17.6 Example of using NAND Flash TMP92CH21 NAND Flash-0 NAND Flash-1 100KΩ NDCLE NDALE /NDRE /NDWE 2KΩ NDR/B R/B (open drain) R/B (open drain) D[7:0] I/O[7:0] I/O[7:0] /ND0CE /ND1CE External circuits for Write-protect (Note1) By reset, both /NDRE and /NDWE pins become input port(Port71 and 72). So, pull-up resisters are needed for them.
Page 389 TMP92CH21 3.18 16-Bit Timer/Event Counters (TMRB) The TMP92CH21 incorporates one multifunctional 16-bit timer/event counter (TMRB0) which have the following operation modes: • 16-Bit Interval Timer Mode • 16-Bit Event Counter Mode 16-Bit Programmable Pulse Generation (PPG) Mode Can be used following operation modes by capture function: •...
Page 390 INT output Register 0 Register 1 Internal data-bus Internal data bus INTTB00 INTTB01 Run/ Clear Prescaler clock: TB0RUN φT0 <TB0PRUN> External INT φT1 φT4 φT16 input Capture Register 0 Caputure register 1 (unused)INT7 TB0CP0H/L TB0CP1H/L Timer flip-flop (unused)INT8 Timer output ...
Page 391 TMP92CH21 3.18.2 Operation (1) Prescaler The 5-bit prescaler generates the source clock for timer 0. The prescaler clock (φT0) is divided clock (divided by 4) from system clock f This prescaler can be started or stopped using TB0RUN<TB0PRUN>. Counting starts when <TB0PRUN>...
Page 392 TMP92CH21 (3) Timer registers (TB0RG0 and TB0RG1) These two 16-bit registers are used to set the interval time. When the value in the up-counter UC0 matches the value set in this timer register, the Comparator Match Detect signal will go Active. Setting data for timer register is executed using 2 byte data transfer instruction or using 1 byte date transfer instruction twice for lower 8 bits and upper 8 bits in order.
Page 393 TMP92CH21 (4) Capture Registers (TB0CP0H/L) These 16-bit registers are used to latch the values in the up-counters. Data in the Capture Registers should be read using a 2-byte data load instruction or two 1-byte data load instructions. The least significant byte is read first, followed by the most significant byte.
Page 394 TMP92CH21 3.18.3 TMRB0 Run Register TB0RUN Bit symbol TB0RDE – I2TB0 TB0RUN TB0PRUN (1180H) Read/Write After Reset Double (Note) IDLE2 Timer Run/Stop control Buffer always 0: Stop 0: Stop & Clear Function 0: Disable fixed to "0" 1: Operate 1: Run (count up) 1: Enable Count operation Stop and Clear...
Page 395 TMP92CH21 TMRB0 Mode Register TB0MOD Bit symbol TB0ET1 TB0CP01 TB0CPM1 TB0CPM0 TB0CLE TB0CLK1 TB0CLK0 (1182H) Read/Write After Reset Capture timing Execute Control up- TMRB0 source clock TB0FF1 software counter 00: reserved inversion 00: Disable capture 0: Disable 01: φT1 0: Disable 01:reserved 0: Execute clearing...
Page 396 TMP92CH21 TMRB0 Flip-Flop Control Register TB0FFCR Bit symbol TB0FF1C1 TB0FF1C0 TB0C0T1 TB0E1T1 TB0E0T1 TB0FF0C1 TB0FF0C0 (1183H) Read/Write After Reset Control TB0FF1 TB0FF0 inversion trigger Control TB0FF0 00: Invert 0: Disable trigger 00: Invert 01: Set 1: Enable trigger 01: Set (Note) 10: Clear 10: Clear...
Page 397 TMP92CH21 3.18.4 Operation in each mode (1) 16-Bit Timer Mode Generating interrupts at fixed intervals In this example, the interrupt INTTB01 is set to be generated at fixed intervals. The interval time is set in the timer register TB0RG1. ← TB0RUN –...
Page 398 TMP92CH21 The following block diagram illustrates this mode. TB0RUN<TB0RUN> TB0OUT0 (PPG output) Selector 16-Bit up-counter φT1 clear φT4 (TB0FF0) φT16 Match 16-Bit Comparator 16-Bit Comparator TB0RG0 Selector TB0RG0-WR Register buffer 0 TB0RG1 TB0RUN<TB0RDE> Internal bus Figure 3.18.7 Block Diagram of 16-BIT Mode The following example shows how to set 16-Bit PPG Output Mode: ←...
Page 399: Touch Screen Interface
TMP92CH21 3.19 Touch Screen Interface (TSI) The TMP92CH21 has an interface for 4-terminal resistor network touch-screen. This interface supports two procedure: an X/Y position measurement and a touch detection. Each procedure can be performed by setting the TSI control register(TSICR0 and TSICR1) and using an internal AD converter.
Page 400 TMP92CH21 3.10.2 Touch Screen Interface (TSI) Control Register TSI Control Register bit Symbol TSI7 PTST TWIEN PYEN PXEN MYEN MXEN TSICR0 (01F0H) Read/W rite After reset 0 : Disable 0 : not 0 : Disable 0 : Disable 0 : Disable 0 : Disable 0 : Disable 1 : Enable...
Page 401 TMP92CH21 3.10.3 Touch detection procedure A touch detection procedure is a preparing procedure till a pen touches to the screen. By touching, TSI generates interrupt(INT4) and this procedure will terminate. After an X/Y position measuring procedure is terminated, return to this procedure and wait for next touch. When the waiting state, ON only SPY-switch and OFF other 3 switches(SMY,SPX and SMX).
Page 402 TMP92CH21 Reset counter for de-bounce period Start counter for de-bounce period De-bounce De-bounce De-bounce period period period INT4 INT4 is generated by matching counter and After pen is de-touched, INT4 can be issued again. specified de-bounce period. INT4 isn’t generated by matching counter and specified de-bounce period because of it is an edge-type interrupt.
Page 403 TMP92CH21 3.10.4 X/Y position measuring procedure In the INT4 routine, execute an X/Y position measuring procedure like below. < X position measurement> At first, ON both SPX and SMX-switches and OFF other 2 switches. By this setting, analog-voltage which shows the X-position will be inputted to PG3/MY/AN3 pin .
Page 404 TMP92CH21 3.10.5 Flow chart for TSI (2)X/Y Position (1)Touch Detection Procedure Measurement Procedure Main Routine: INT4 Routine: TSICR0←98H TSICR1←XXH(voluntary) <X position measurement> ･TSICR0←85H ･AD conversion for AN3 Execute Main Routine ･Store the result <Y position measurement> ･TSICR0←8AH ･AD conversion for AN2 ･Store the result Execute an operation By using X/Y-position...
Page 405 TMP92CH21 3.20 I S (Inter-IC Sound) A serial-output circuit with I S-format compatible is built-in. This product can be used for the digital audio system application by connecting LSI for voice generation (ex. D/A Converter). This circuit has both I S-mode and general SIO-mode.
Page 406 TMP92CH21 3.20.1 Block diagram prescaler I2SCKO I2SCKO control <MCK1:0> <TXE,CLKE> ÷4 I2SWS I2SWS control TA1OUT <I2SWCK> <FMT,I2SWLVL> <BUSY> 16Byte FIFO(Right) <DIR> 16bit (2Byte × 8) Write Pointer Data Selector, FIFO control Interrupt- Read Pointer control I2SDO 16Byte FIFO(Left) 16bit (2Byte × 8) INTI2S <FMT>...
Page 407 TMP92CH21 3.20.2 SFR The following tables are SFR for I2S. This I2S are connected to CPU with 16-bit data bus. So, when CPU access SFR, the 2-byte load-instruction should be used. I2SCTL0 Register bit Symbol BUSY MCK1 MCK0 I2SWCK Read/Write I2SCTL0 After reset (080EH)
Page 408 TMP92CH21 3.20.3 Explanation of I S-mode (1) Connection example Figure 3.20.3(1) shows an example with external-LSI. TMP92CH21 (TRANSMITTER) (RECEIVER) P92/I2SWS P90/I2SCKO P91/I2SDO DATA Ex) D/A Converter Note) Since P90 to P92 become High-impedance, connect pull-up or pull-down resistor if necessary. Figure 3.20.3(1) ...
Page 409 TMP92CH21 Write to FIFO <TXE> I2SWS-pin I2SCKO-pin I2SDO-pin <BUSY> INTI2S Figure 3.20.3(2) Whole timing diagram I2SWS-pin 10MHz I2SCKO-pin I2SDO-pin Bit7 Bit6 Bit0 Bit7 Bit6 Bit7 Bit0 Figure 3.20.3(3) Detail timing diagram (3) Notes 1) INTI2S timing INTI2S is generated after the last data in FIFO is loaded to the internal shifter. ...
Page 410 TMP92CH21 3.20.4 Explanation of SIO-mode (1) Connection example Figure 3.20.4(1) shows an example with external-LSI. TMP92CH21 (TRANSMITTER) (RECEIVER) P90/I2SCKO P91/I2SDO Port Ex. Shift register Note) Since P90 to P91 become High-impedance, connect pull-up or pull-down resistor if necessary. Figure 3.20.3(1) example with external-LSI (2) Procedure The 32byte-FIFO are built-in and if a FIFO’s data became empty, INTI2S-interrupt is occurred.
Page 411 TMP92CH21 Write to FIFO <TXE> I2SCKO-pin I2SDO-pin <BUSY> INTI2S Figure 3.20.4(2) Whole timing 10MHz I2SCKO-pin I2SDO-pin Bit0 Bit1 Bit7 Bit0 Bit1 Bit7 Figure 3.20.4(2) Detail timing (3) Notes 1) INTI2S timing INTI2S is generated after the last data in FIFO is loaded to the internal shifter. ...
Page 412 TMP92CH21 3.21 Boot ROM for 1 -cut The Boot ROM is built-in to download user’s boot-program. The 3-kind of downloading way are supported. (Notes) There are some limitations for the 1 -cut sample’s boot-program. They are shown by red-color. Please be careful about them. 3.21.1 Operation mode There are 2 operation mode : MULTI-mode, BOOT-mode.
Page 413 TMP92CH21 3.21.2 Hardware specification about internal Boot-ROM (1) Memory map Figure 3.21.3 shows a memory map of BOOT-mode. An 8Kbyte ROM is built-in and it is mapped 3FE000H to 3FFFFFH address. At MULTI-mode, boot-ROM is not mapped and its area is mapped as external area. 000000H Internal-I/O 002000H...
Page 414 TMP92CH21 3.21.3 Outline of boot-operation There are 3 kinds of downloading way: NAND-Flash, UART and USB. After reset, a boot-program in the boot-ROM operate like following flow-chart. START Clock setting ・f OSCH ・f * 16/3 OSCH Check NAND-FLASH OK ? Download from NAND-Flash Check...
Page 415 TMP92CH21 Download from NAND-Flash 3.21.4 (1) Connection example Figure 3.21.4(1) shows an example of NAND-Flash with 16-bit SDRAM. P84,/ND0CE PJ6,NDCLE PJ5,NDALE TMP92CH21 P71,/NDRE P72,/NDWE P75,NDR/B PF7,SDCLK NAND-Flash PJ7,SDCKE PJ2,/SDCS PJ0,,/SDRAS /RAS PJ1,/SDCAS /CAS PJ2,/SDWE LLDQM PJ3,SDLLDQM PJ4,SDLUDQM LUDQM IO0〜IO7 SDRAM A0〜A12 A0〜A11,BS0 D0〜D15...
Page 416 TMP92CH21 (3) Data assignment The download data are consist of boot identification code(4Byte),user-program size(2Byte) and user-program(max.10Kbyte). They should be assigned(programmed) in NAND-Flash like Figure 3.21.4(2). Address : 511(or 255) Page-0 boot Page-1 Block-0 identification code(4Byte) Page-end user-program size(2Byte) Page-0 Page-1 Block-1 user-program (max.10KByte)
Page 417 TMP92CH21 ser-program (max.10KByte) An user-program is loaded to internal-RAM. Be careful the start address is 3000H to make user-program. Beforehand, program(write) an user-program to NAND-Flash in Binary-format. The below is an example to explain how to make binary-format file. (Example) How to convert from extended intel-HEX format file to Binary-format file The following is an example of display in text-editor in case of intel-HEX format file is opened.
Page 418 TMP92CH21 (4) Error check item The below are checked items by a boot-program. If any error occurs in each check, a boot-program will cancel downloading from NAND-Flash and skip to next(UART) operation. a) Usable NAND-Flash The boot-program reads a device-code from NAND-Flash and checks whether it is usable or not.
Page 419 TMP92CH21 (6) Port setting The boot-program set some ports which are shown in Table 3.21.4(2) to function ports. Another ports are not set, so they are kept after reset status. It is needed to care these ports to design an application system. Table 3.21.4(2) Settled Ports Pin name After reset...
Page 420 TMP92CH21 3.21.5 Download with UART 1) Connection example Figure 3.21.5 shows an example of UART with 16-bit NOR-Flash. UART 3pin Level TXD1,PF0 (out) Shifter RXD1,PF1 (in) P82,/CS2 /RTS PC7,/CSZF,LCP1(out) P70,/RD PJ2,/SRWR NOR-Flash TMP92CH21 D0〜D15 D0〜D15 A0〜A19 A1〜20 (Note1) By reset, both TXD0, RXD0 and /RTS become input port(PortF0,F1 and PC7). If necessary, Add pull-up or pull-down resistor.
Page 421: Boot Rom
TMP92CH21 3) UART data transfer format Table 3.21.5(1) to (6) show supported frequency, data transfer format, baud rate modification commands, operation commands, version management information, and frequency measurement result with data storing location, respectively. Also refer to the description of boot-program operation in the later pages of this chapter as you read these tables.
Page 422 TMP92CH21 Table3.21.5(3) Baud rate modification command Baud Rate (bps) 9600 19200 38400 57600 115200 Modification command (Note1) When f (oscillation frequency) is either 16.00,20.00,20.58 or 25MHz, a 115200bps baud-rate is not supported. OSCH (Notes2) For the 1 -cut sample, the baud-rate can not be changed . Table3.21.5(4) Operation command Operation command Operation...
Page 423 TMP92CH21 The 7th byte is used to send information of the measured frequency. The PC should check that the frequency of the resonator is measured correctly. The receive data in the 8th byte is the baud rate modification data. The five kinds of baud rate modification data shown in Table are available.
Page 424 TMP92CH21 b) Error code The boot-program sends the processing status to PC using various code. The error code is listed in the table below. Table3.21.5(7) Error code Error Code Meaning of Error Code Baud rate modification error occurred. Operation command error occurred. Framing error in received data occurred.
Page 425 TMP92CH21 d) Notes on extended intel-hex format (binary) After receiving the checksum of a record, the device waits for the start mark (3AH for “:”) of the next record. Therefore, the device ignores all data received between records during that time unless the data is 3AH. Make sure that once the controller program has finished sending the checksum of the end record, it does not send anything and waits for two byes of data to be received (upper and lower bytes of SUM).
Page 426 TMP92CH21 The intel-HEX format and its meaning are below. Data record 3A 10 3000 00 0607F100030000F201030000B1F16010 B7 Data Checksum Record type Address Data number : (Start mark) End record 3A 00 0000 01 FF Data Record type Address Data number : (Start mark) 92CH21-422...
Page 427 TMP92CH21 e) Error when receiving user-program If the following errors occur in extended intel-hex format when receiving the user-program, the device goes to an idle state. • When the record type is not 00H, 01H, 02H • When a checksum error occurs f) Error between frequency measurement and baud rate The boot-program measures the resonator frequency when receiving matching data.
Page 428 TMP92CH21 5) Port setting Only ports shown in Table 3.21.4(2)3.21.5(9) are set up in the boot-program. Another ports are not set, so they are kept after reset status. It is needed to care these ports to design an application system. Table 3.21.5(9) Settled Ports Pin name After reset...
Page 429 TMP92CH21 3.21.6 Download with USB 1) Connection example Figure 3.21.6(1) shows an example of USB with 16-bit NOR-Flash. PUCTL PC6,KO8,LDIV R1=1.5K Ω P82,/CS2 P70,/RD PJ2,/SRWR NOR-Flash TMP92CH21 D0 〜 D15 D0 〜 D15 A0 〜 A19 A1 〜 20 (Note1) By reset, PC6 become input port.
Page 430: Power Supply Backup
TMP92CH21 3.22 PSB (Power Supply Backup) The power supply input of TMP92CH21 is divided into three systems as follows; Analog Power supply input (AVCC - AVSS) Digital Power supply input (DVCC - DVSS) Digital power supply input for RTC (RTCVCC - DVSS) The individual power supply input is isolated from each other.
Page 431 TMP92CH21 The TMP92CH21 has the power supply backup mode which is designed to work for only RTC under sub battery supply. TMP92CH21 enters the power supply backup mode using the /BE(Backup enable signal Pin) and the /RESET.
Page 432: Electrical Charactoristics
TMP92CH21 Tentative 4. Electrical Characteristics 4.1 Absolute Maximum Ratings Parameter Symbol Rating Unit -0.5 to 4.0 Power Supply Voltage V CC -0.5〜VCC+0.5 Input Voltage V IN Output Current Output Current Output Current(total) Σ IOL Output Current(total) Σ IOH Power Dissipation(Ta=85℃) Soldering Temperature(10s) ℃...
Page 433 TMP92CH21 4.2 DC Electrical Characteristics Vcc = 3.3 ± 0.3V / X1 = 8 to 40MHz / Ta = -20 to 70℃ Symbol Parameter Typ. Unit Condition Power Supply Voltage X1=8 to 40MHz (DVCC=AVCC=RTCVCC) (Internal 8 to 20MHz) (DVSS=AVSS=0V) XT1=30 to 34KHz Input Low Voltage for D0 to D7 VIL0...
Page 434 TMP92CH21 Vcc = 3.3 ± 0.3V / X1 = 8 to 40MHz / Ta = -20 to 70℃ Symbol Parameter Typ. Unit Condition Output Low Voltage 0.45 IOL = 1.6mA IOH = -400μA VOH1 Output High Voltage IOH = -100μA VOH2 0.75*VCC IOH = -20μA...
Page 435 TMP92CH21 4.3 AC Characteristics 4.3.1 Basic Bus Cycle Read cycle Vcc = 3.3 ± 0.3V / X1 = 8 to 40MHz / Ta = -20 to 70℃ Parameter Symbol 40MHz 36MHz Unit OSC period (X1/X2) 31.25 27.7 System Clock period (=T) 62.5 55.5 SDCLK Low Width...
Page 436 TMP92CH21 (1) Read cycle (0 wait) SDCLK /WAIT A0 to A23 /CSn D0 to D31 Data Input /SRxxB /SRWR Note: The phase relation between X1 input signal and the other signals is undefined. The timing chart above is an example. 92CH21-432...
Page 437 TMP92CH21 (2) Write cycle (0 wait) SDCLK /WAIT A0 to A23 /CSn /WRxx D0 to D31 Data Output /SRxxB /SRWR Note: The phase relation between X1 input signal and the other signals is undefined. The timing chart above is an example. 92CH21-433...
Page 438 TMP92CH21 (3) Read cycle (1 wait) SDCLK /WAIT A0 to A23 /CSn D0 to D31 Data Input (4) Write cycle (1 wait) SDCLK /WAIT A0 to A23 /CSn /WRxx D0 to D31 Data Output 92CH21-434...
Page 439 TMP92CH21 4.3.2 Page ROM Read Cycle (1)3-2-2-2 mode Vcc = 3.3 ± 0.3V / X1 = 8 to 40MHz / Ta = -20 to 70℃ Symbol Parameter 40MHz 36MHz Unit System Clock Period (=T) 62.5 A0,A1 → D0 to D31 Input 2.0T-50 A2 to A23 →...
Page 440 TMP92CH21 4.3.3 SDRAM Controller AC Characteristics Vcc = 3.3 ± 0.3V / X1 = 8 to 40MHz / Ta = -20 to 70℃ Symbol Parameter Variable 40MHz 36MHz Unit Ref/Active Ref/Active Command Period Active to Precharge Command Period 12210 12210 12210 Active to Read/Write Command Delay 55.5...
Page 441 TMP92CH21 (1) SDRAM Read Timing (CPU Access or LCDC Normal Access) SDCLK SDxxDQM /SDCS /SDRAS /SDCAS /SDWE 16bit data bus A1-10 Column Column A12-15 Column D0-15 Data-in 32bit data bus A1-11 Column Column Column A13-15 Data-in D0-31 92CH21-437...
Page 442 TMP92CH21 (2) SDRAM Write Timing (CPU Access) SDCLK SDxxDQM /SDCS /SDRAS /SDCAS /SDWE 16bit Data bus A1-12 Column Column A12-15 Column D0-15 Data-out 32bit Data bus Column A1-11 Column Column A13-15 D0-31 Data-out 92CH21-438...
Page 443 TMP92CH21 (3) SDRAM Burst Read Timing (Start of Burst Cycle) SDCLK SDxxDQM /SDCS /SDRAS /SDCAS /SDWE Column A1-11orA1-10 Column A12orA11 A13-15orA12-15 Data-in Data-in D0-31 Data-in 92CH21-439...
Page 444 TMP92CH21 (4) SDRAM Burst Read Timing (End of Burst Cycle) SDCLK SDxxDQM /SDCS /SDRAS /SDCAS /SDWE Column Column A1-11orA1-10 Column Column A12orA11 Column A13-15orA12-15 Data-in D0-31 Data-in Data-in 92CH21-440...
Page 445 TMP92CH21 (5) SDRAM Initialize Timing SDCLK SDxxDQM /SDCS /SDRAS /SDCAS /SDWE A1-12 A20-23 (BS0,1) 92CH21-441...
Page 446 TMP92CH21 (6) SDRAM Refresh Timing SDCLK SDxxDQM /SDCS /SDRAS /SDCAS /SDWE (7) SDRAM Self Refresh Timing SDCLK SDCKE SDxxDQM /SDCS /SDRAS /SDCAS /SDWE 92CH21-442...
Page 447 TMP92CH21 4.3.4 NAND-Flash Controller AC Characteristics Vcc = 3.3 ± 0.3V / X1 = 8 to 40MHz / Ta = -20 to 70℃ Symbol Parameter Variable 40MHz 36MHz Unit /NDRE Low width T-12 /NDRE Data access time T-15 Read data hold time /NDWE Low width 0.75T-12 Write data set-up time...
Page 448 TMP92CH21 4.4 AD Conversion Characteristics Symbol Parameter Unit Analog reference voltage(＋) VREFH VCC-0.2 Analog reference voltage(−) VREFL VSS+0.2 AVCC AD Converter Power Supply Voltage AVSS AD Converter Ground AVIN Analog Input Voltage VREFL VREFH IREF Analog Current for analog reference voltage 1.35 <VREFON>...
Page 449 TMP92CH21 4.6 Interrupt Operation Variable 40MHz 36MHz Parameter Symbol Unit INT0〜INT5 Low Width 4T+40 INTAL INT0〜INT5 High Width 4T+40 INTAH 4.7 LCD Controller (SR mode) D1BSCP LD0 to 7 LD0 to 7 out Vcc = 3.3 ± 0.3V / X1 = 8 to 40MHz / Ta = -20 to 70 ℃ Variable 40 MHz 32 MHz...
Page 450 TMP92CH21 4.8 I S timing (I S,SIO-mode) Variable 40 MHz 36 MHz Unit Symbol Parameter I2SCKO Period I2SCKO High width - 10 I2SCKO Low width - 10 I2SDO,I2SWS setup time - 13 I2SDO,I2SWS hold time AC Measuring Conditions : High = 0.7 Vcc, Low = 0.3 Vcc, CL = 10 pF Output Level ...
Page 451 TMP92CH21 4.12 Recommended Crystal Oscillation Circuit TMP92CH21 is evaluated by below oscillator vender. When selecting external parts, make use of this information.. (note): Total loads value of oscillator is sum of external loads(C1 and C2) and floating loads of actual assemble board. There is a possibility of miss-operating using C1 and C2 value in below table.
Page 452: Table Of Speial Function Registers (Sfrs)
TMP92CH21 Table of Special function registers (SFRs) (SFR ; special function register) The SFRs include the I/O ports and peripheral control registers allocated to the 4K bytes address space from 000000H to 001FFFH. (1)I/O Port (11) UART/Serial Channel (2)Interrupt Control (12) USB Controller (3)Memory Controller (13) AD Converter...
Page 453 TMP92CH21 Table 5 I/O register address map [1] PORT NAME NAME NAME NAME ADDRESS ADDRESS ADDRESS ADDRESS 0000H 0010H 0020H 0030H P8FC2 PCCR P4FC P8FC PCFC P9FC2 P1CR P9CR P1FC P5FC P9FC P2FC2 P2CR P6CR PACR P2FC P6FC PAFC PFFC2 P3CR P7CR PFCR...
Page 454 TMP92CH21 [2] INTC NAME NAME NAME NAME ADDRESS ADDRESS ADDRESS ADDRESS 00D0H INTE12 00E0H Reserved 00F0H INTE0AD 0100H DMA0V INTE34 Reserved INTETC01 DMA1V Reserved INTETC23 DMA2V INTEUSB INTETC45 DMA3V INTETA01 Reserved INTETC67 DMA4V INTETA23 INTALM01 SIMC DMA5V INTALM23 IIMC DMA6V INTALM4 INTWDT DMA7V...
Page 455 TMP92CH21 [5] CGEAR,PLL [6] LCDC-1 ADDRES NAME NAME NAME ADDRESS ADDRESS 10E0H SYSCR0 0280H LCDMODE0 0290H SYSCR1 LCDMODE1 LCDRP10 SYSCR2 LCDFFP LCDRP32 EMCCR0 LCDDVM LCDRP54 EMCCR1 LCDSIZE LCDRP76 EMCCR2 LCDCTL0 LCDGP10 Reserved LCDCTL1 LCDGP32 LCDSCC LCDGP54 PLLCR0 LCDCCR0 LCDGP76 PLLCR1 LCDCCR1 LCDBP10 LCDCCR2...
Page 456 TMP92CH21 [7] TSI [8] SDRAMC [9] 8bit Timer [10] 16bit Timer NAME NAME NAME NAME ADDRESS ADDRESS ADDRESS ADDRESS 01F0H TSICR0 0250H SDACR1 1100H TA01RUN 1180H TB0RUN TSICR1 SDACR2 SDRCR TA0REG TB0MOD SDCMM TA1REG TB0FFCR TA01MOD TA01FFCR TA23RUN TB0RG0L TB0RG0H TA2REG...
Page 457 TMP92CH21 [12] USB Controller (1/2) ADDRES ADDRES ADDRES NAME NAME NAME NAME ADDRESS 0500H Descripter- 0780H ENDPOINT0 0790H EP0_STATUS 07A0H ENDPOINT1 EP1_STATUS EP1_SIZE_L_B 067FH (384Byte) ENDPOINT2 EP2_STATUS EP2_SIZE_L_B ENDPOINT3 EP3_STATUS EP3_SIZE_L_B EP0_SIZE_L_A EP1_MODE EP1_SIZE_L_A EP1_SIZE_H_A EP2_SIZE_L_A EP2_SIZE_H_A EP2_MODE EP3_MODE EP3_SIZE_L_A EP3_SIZE_H_A NAME NAME...
Page 458 TMP92CH21 [12] USB Controller (2/2) NAME NAME ADDRESS ADDRESS 07E0H Port_Status 07F0H USBINTFR1 FRAME_L USBINTFR2 FRAME_H USBINTFR3 ADDRESS USBINTFR4 USBINTMR1 USBINTMR2 USBREADY USBINTMR3 USBINTMR4 SetDescriptorSTALL USBCR1 Note: Do not access no-allocated name address. 92CH21 - 455...
Page 459 TMP92CH21 [13] 10bit ADC [14] WDT NAME NAME NAME ADDRESS ADDRESS ADDRESS 12A0H ADREG0L 12B0H 1300H WDMOD ADREG0H WDCR ADREG1L ADREG1H ADREG2L ADREG2H ADREG3L ADREG3H Reserved ADMOD0 Reserved ADMOD1 Reserved ADMOD2 Reserved Reserved Reserved Reserved Reserved Reserved [15] RTC [16] MLD NAME NAME...
Page 460 TMP92CH21 [17] NAND-Flash Controller-1 NAME NAME NAME NAME ADDRESS ADDRESS ADDRESS ADDRESS 1CC0H 1CD0H ND0FIMR 1CE0H 1CF0H ND1FIMR ND0FMCR ND0FSPR ND1FMCR ND1FSPR ND0FSR ND0FRSTR ND1FSR ND1FRSTR ND0FISR ND1FISR NAME NAME NAME ADDRESS ADDRESS ADDRESS ND0ECCRD 1D00H ND0FDTR, 1CB0H 01C0H NDCR ND1ECCRD ND1FDTR 1EFFH...
Page 461 TMP92CH21 [18] I NAME ADDRESS 0800H I2SBUFR I2SBUFL I2SCTL0 Note: Do not access no-allocated name address. 92CH21 - 458...
Page 462 TMP92CH21 (1) I/O Ports (1/6) SYMBOL NAME Address PORT1 0004H Input Mode PORT2 0008H Input Mode PORT3 000CH Input Mode PORT4 0010H Output Mode PORT5 0014H Output Mode PORT6 0018H Input Mode PORT7 001CH Input Output Input Mode Output Mode PORT8 0020H PORT9...
Page 463 TMP92CH21 (1) I/O Ports (2/6) SYMBOL NAME Address P17C P16C P15C P14C P13C P12C P11C P10C PORT1 P1CR Control 0006H Register 0:Input 1:Output PORT1 P1FC Function 0007H Register 0:PORT 1:Data Bus(D8 to D15) P27C P26C P25C P24C P23C P22C P21C P20C PORT2 P2CR...
Page 464 TMP92CH21 (1) I/O Ports (3/6) SYMBOL NAME Address P76C P75C P72C P71C PORT7 P7CR Control 001EH Register 0:Input 1:Output P76F P75F P74F P73F P72F P71F P70F PORT7 Function P7FC 001FH 0:PORT 0:PORT 0:PORT Register 0:PORT 0:PORT 0:PORT 0:PORT 1:/WAIT 1:/WRLU 1:/WRLL 1:R/W 1:EA25...
Page 465 TMP92CH21 (1) I/O Ports (4/6) SYMBOL NAME Address PF4C PF3C PF2C PF1C PF0C PORTF PFCR Control 003EH Register 0: IN 1: OUT PF7F PF4F PF3F PF2F PF1F PF0F PORTF PFFC Function 003FH Register 0: port SDCLK PF4F2 PF3F2...
Page 466 TMP92CH21 (1) I/O Ports (5/6) SYMBOL NAME Address P17D P16D P15D P14D P13D P12D P11D P10D PORT1 P1DR 0081H Drive Register Output/Input buffer drive-register for standby-mode P27D P26D P25D P24D P23D P22D P21D P20D PORT2 P2DR Drive 0082H Register Output/Input buffer drive-register for standby-mode P37D P36D P35D...
Page 467 TMP92CH21 (1) I/O Ports (6/6) SYMBOL NAME Address PK3D PK2D PK1D PK0D PORTK PKDR Drive 0094H Register Output/Input buffer drive-register for standby-mode PL7D PL6D PL5D PL4D PL3D PL2D PL1D PL0D PORTL PLDR 0095H Drive Register Output/Input buffer drive-register for standby-mode PM2D PM1D PM0D...
Page 468 TMP92CH21 (2) Interrupt Control(1/4) Symbol NAME Address INT2 INT1 INT1 & INT2 I2M2 I2M1 I2M0 I1M2 I1M1 I1M0 INTE12 00D0H Enable INT4 INT3 INT3 & INT4 I4M2 I4M1 I4M0 I3M2 I3M1 I3M0 INTE34 00D1H Enable INTTA1(Timer1) INTTA0(Timer0) INTTA0 & INTTA1 ITA1C ITA1M2 ITA1M1...
Page 469 TMP92CH21 (2) Interrupt Control(2/4) Symbol NAME Address INTALM4 INTALM4 IA4C IA4M2 IA4M1 IA4M0 INTEALM4 00E7H Enable Note: Always fixed to 0 INTRTC INTRTC IRM2 IRM1 IRM0 INTERTC 00E8H Enable Note: Always fixed to 0 INTKEY INTKEY IKM2 IKM1 IKM0 INTECKEY 00E9H Enable Note: Always fixed to 0...
Page 470 TMP92CH21 (2) Interrupt Control(3/4) Symbol NAME Address INTAD INT0 INT0 & INTAD IADC IADM2 IADM1 IADM0 I0M2 I0M1 I0M0 INTE0AD 00F0H Enable INTTC1(DMA1) INTTC0(DMA0) INTTC0 & ITC1C ITC1M2 ITC1M1 ITC1M0 ITC0C ITC0M2 ITC0M1 ITC0M0 INTETC01 00F1H INTTC1 Enable INTTC3(DMA3) INTTC2(DMA2) INTTC2&...
Page 471 TMP92CH21 (2) Interrupt Control(4/4) Symbol NAME Address DMA0V5 DMA0V4 DMA0V3 DMA0V2 DMA0V1 DMA0V0 DMA0 DMA0V Start 0100H Vector DMA0 Start Vector DMA1V5 DMA1V4 DMA1V3 DMA1V2 DMA1V1 DMA1V0 DMA1 DMA1V Start 0101H Vector DMA1 Start Vector DMA2V5 DMA2V4 DMA2V3 DMA2V2 DMA2V1 DMA2V0 DMA2 DMA2V...
Page 472 TMP92CH21 (3) Memory Controller(1/2) Symbol NAME Address B0WW2 B0WW1 B0WW0 B0WR2 B0WR1 B0WR0 BLOCK 0 CS/WAIT Write waits Read waits B0CSL Control 0140H 001:0WAIT 010:1WAIT 001:0WAIT 010:1WAIT Register 101:2WAIT 110:3WAIT 101:2WAIT 110:3WAIT 011:1+NWAIT 111:4WAIT 011:1+NWAIT 111:4WAIT Others:Resrved Others:Resrved B0REC B0OM1 B0OM0 B0BUS1 B0BUS0...
Page 473 TMP92CH21 (3) Memory Controller(2/2) Symbol NAME Address BEXWW2 BEXWW1 BEXWW0 BEXWR2 BEXWR1 BEXWR0 BLOCK CS/WAIT BEXCSL 0158H Write waits Read waits Control 001:2WAIT 010:1WAIT 001:2WAIT 010:1WAIT Register 101:2WAIT 110:2WAIT 101:2WAIT 110:2WAIT 011:1+NWAIT Others:Resrved 011:1+NWAIT Others:Resrved BEXOM1 BEXOM0 BEXBUS1 BEXBUS0 BLOCK CS/WAIT BEXCSH 0159H...
Page 474 TMP92CH21 (4) MMU Symbol NAME Address LOCALX Register LOCALPX 01D0H LOCALX Program Setting BANK number for LOCALX 1: enable LOCALY Register LOCALPY 01D1H LOCALY Setting BANK number for LOCALY Program 1: enable LOCALZ Register LOCALPZ 01D3H LOCALZ Setting BANK number for LOCAL2 Program 1: enable LOCALX...
Page 475 TMP92CH21 (5) Clock Gear,PLL Symbol NAME Address XTEN WUEF System Clock SYSCR0 10E0H Control H-OSC(fc) L-OSC(fs) Warm-up 0: stop 0: stop Timer Register0 oscillation oscillation SYSCK GEAR2 GEAR1 GEAR0 System Clock Select Select gear value of high frequency (fc) SYSCR1 10E1H Control system...
Page 476 TMP92CH21 (6) LCD Controller(1/6) Symbol Name Address RAMTYPE RAMTYPE0 SCPW1 SCPW0 MODE3 MODE2 MODE1 MODE0 Mode0 0280H MODE0 Register LDINV AUTOINV LDO1 LDO0 Mode1 0281H MODE1 Register Frame LCDFFP Frequenc 0282H Register Setting bit7-0 for f FP FMN7 FMN6 FMN5 FMN4 FMN3 FMN2...
Page 477 TMP92CH21 (6) LCD Controller(2/6) Symbol Name Address SCC7 SCC6 SCC5 SCC4 SCC3 SCC2 SCC1 SCC0 Sourcer LCDSCC Clock 0287H Counter Register LCDC Source Clock Counter bit7-0 PCPV2 PCPV1 PCPV0 Clock LCDCCR0 Counter 0288H Register TLDE4 TLDE3 TLDE2 TLDE1 TLDE0 Clock LCDCCR1 Counter 0289H...
Page 478 TMP92CH21 (6) LCD Controller(3/6) Symbol Name Address Green LCDGP10 Palette 0295H Register Green LCDGP32 Palette 0296H Register Green LCDGP54 Palette 0297H Register Green LCDGP76 Palette 0298H Register Blue LCDBP10 Palette 0299H Register Blue LCDBP32 Palette 029AH Register 92CH21 - 475...
Page 479 TMP92CH21 (6) LCD Controller(4/6) Symbol Name Address Start Address LSARAL 02A0H Register A-Area(L) Start Address for A-area(bit7-0) SA15 SA14 SA13 SA12 SA11 SA10 Start Address LSARAM 02A1H Register A-Area(M) Start Address for A-area(bit15-8) SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 Start Address...
Page 480 TMP92CH21 (6) LCD Controller(5/6) Symbol Name Address OE007 OE006 OE005 OE004 OE003 OE002 OE001 OE000 LCDOE00 02B0H Control Register-0 OE017 OE016 OE015 OE014 OE013 OE012 OE011 OE010 LCDOE01 02B1H Control Register-1 OE027 OE026 OE025 OE024 OE023 OE022 OE021 OE020 LCDOE02 02B2H Control Register-2...
Page 481 TMP92CH21 (6) LCD Controller(6/6) Symbol Name Address OE207 OE206 OE205 OE204 OE203 OE202 OE201 OE200 LCDOE20 02D0H Control Register-0 OE217 OE216 OE215 OE214 OE213 OE212 OE211 OE210 LCDOE21 02D1H Control Register-1 OE227 OE226 OE225 OE224 OE223 OE222 OE221 OE220 LCDOE22 02D2H Control Register-2...
Page 482 TMP92CH21 (7) Touch Screen I/F Symbol Name Address PTST TWIEN PYEN PXEN MYEN MXEN TSI7 Touch TSICR0 Screen I/F 01F0H Control Reg0 0: Disable 0: not 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 1: Enable touch 1: Enable 1: Enable 1: Enable 1: Enable...
Page 483 TMP92CH21 (9) 8-bit Timer Symbol NAME Address TA0RDE I2TA01 TA1RUN TA0RUN TA01PRUN TMRA01 TA01RUN 1100H Double IDLE2 Timer Run/Stop control Register buffer 0: Stop 0: Stop & Clear 0: Disable 1: Operate 1: Run (count up) 1: Enable 8bit Timer TA0REG 1102H Regisster...
Page 484 TMP92CH21 (10) 16-bit Timer Symbol NAME Address TB0RDE – I2TB0 TB0PRUN TB0RUN TMRB0 Double always IDLE2 Timer Run/Stop control TB0RUN 1180H Buffer fixed to 0: Stop 0: Stop & Clear Register "0" 1: Run (count up) Disable Operate 1: Enable TB0ET1 TB0CP01 TB0CLE...
Page 485 TMP92CH21 (11) UART/Serial Channel(1/2) Symbol Name Address Serial Channel 0 SC0BUF 1200H R(Receiving) / W(Transmission) Buffer Register Undefined EVEN OERR PERR FERR SCLKS R (Clear 0 after reading) Serial Channel 0 SC0CR 1201H Receive Parity Parity 1:Error 0: Baud 0:SCLK0↑ Control Rate data...
Page 486 TMP92CH21 (11) UART/Serial Channel(2/2) Symbol Name Address Serial Channel 1 SC1BUF 1208H R(Receiving) / W(Transmission) Buffer Register Undefined EVEN OERR PERR FERR SCLKS R (Clear 0 after reading) Serial Channel 1 SC1CR 1209H Receive Parity Parity 1:Error 0: Baud 0:SCLK1↑ Control Rate data...
Page 487 TMP92CH21 (12) USB Controller (1/) 92CH21 - 484...
Page 488 TMP92CH21 (13) AD Converter(1/2) Symbol Name Address EOCF ADBF ITM0 REPET SCAN AD Mode 0: Every Scan mode Fix to “0” Fix to “0” Repeat ADMOD Control 12B8H Conversion Conversion 1 time 0:Fixed Conversion mode Register 0 End Flag BUSY Flag 1: Every channel start...
Page 489 TMP92CH21 (14) Watchdog Timer Symbol Name Address − WDTE WDTP1 WDTP0 I2WDT RESCR Select detecting time Always IDLE2 Always Mode WDMOD 1300H control 00: 2 fixed to “0”. 0: Stop Internally write 0 Register 1: enable 01: 2 1: Operate connects 10: 2 WDT out...
Page 490 TMP92CH21 (15) RTC (Real–Time Clock) Symbol Name Address Second SECR Register 1320H Undefined “0” 40 sec. 20 sec. 10 sec. 8 sec. 4 sec. 2 sec. 1 sec. Minute MINR Register 1321H Undefined “0” 40 min. 20 min. 10 min. 8 min.
Page 491 TMP92CH21 (16) Melody/Alarm Generator Symbol Name Address Alarm – Pattern 1330H Alarm –Pattern set ALMINV MELALM Melody/ Alarm 1331H MELALMC Control Free-run counter Control Alarm Output 00: Hold Frequency Frequency Always write 0 01: Restart Invert 0: Alarm 10: Clear 1: Invert 1: Melody 11: Clear &...
Page 492 TMP92CH21 (17) NAND Flash Controller(1/2) Symbol Name Address NAND- Flash ND0FDTR 1D00H Data Undefined Transfer Data window to read/write NAND Flash Register ECC1 ECC0 PCNT1 PCNT0 NAND- Flash ND0FMCR 1CC4H Mode Control Register BUSY NAND- Flash ND0FSR 1CC8H Undefined Status 0: ready Register 1: busy...
Page 493 TMP92CH21 (17) NAND Flash Controller(2/2) Symbol Name Address NAND- Flash ND1FDTR 1D00H Data Undefined Transfer Data window to read/write NAND Flash Register ECC1 ECC0 PCNT1 PCNT0 NAND- Flash ND1FMCR 1CE4H Mode Control Register BUSY NAND- Flash ND1FSR 1CE8H Undefined Status 0: ready Register 1: busy...
Page 494 TMP92CH21 (18) I Symbol Name Address R15/R7 R14/R6 R13/R5 R12/R4 R11/R3 R10/R2 R9/R1 R8/R0 FIFO I2SBUFR 0800H Buffer Undefined Register for transmitting buffer(FIFO) (Right-channel) L15/L7 L14/L6 L13/L5 L12/L4 L11/L3 L10/L2 L9/L1 L8/L0 FIFO I2SBUFL 0808H Buffer Undefined Register for transmitting buffer(FIFO) (Left-channel) BUSY MCK1 MCK0...
Page 495 TMP92CH21 6. PACKAGE for TMP92CH21FG Package Name：P-LQFP144-1616-0.40 Unit : mm 18.0±0.2 16.0±0.1 1.0TYP 0.18±0.035 1.0TYP 0.07 M 0.08 17.0±0.2 0.25 0~10 ° (0.5) 0.45~0.75 92CH21-...

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