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Manuals and User Guides for Toshiba TXZ+ Series. We have
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Toshiba TXZ+ Series manuals available for free PDF download: Reference Manual
Toshiba TXZ+ Series Reference Manual (88 pages)
32-bit RISC microcontroller, Clock Control and Operation Mode CG-M4G(1)-C
Brand:
Toshiba
| Category:
Microcontrollers
| Size: 2 MB
Table of Contents
Table of Contents
2
Preface
7
Related Document
7
Conventions
8
Terms and Abbreviations
10
Clock Control and Operation Mode
11
Outlines
11
Clock Control
11
Clock Type
11
The Initial Value by a Reset Action
12
Clock System Diagram
13
Figure 1.1 Clock System Diagram
13
Warming up Function
14
The Warming up Timer for a High Speed Oscillation
14
The Warming up Timer for a Low Speed Oscillation
15
The Directions for a Warming up Timer
15
Clock Multiplying Circuit (PLL) for Fsys
16
PLL Setup after Reset Release
16
The Formula and the Example of a Setting of a PLL Multiplication Value
16
Table 1.1 Details of a [CGPLL0SEL] <PLL0SET [23:0]>Setup
16
Change of the PLL Multiplication Value under Operation
17
Table 1.2 PLL Correction (Example)
17
Table 1.3 PLL0SET Setting Value (Example)
17
PLL Operation Start / Stop / Switching Procedure
18
System Clock
19
Table 1.4 Clock Domains of CPU and Peripherals
19
Table 1.5 Time Interval for Changing System Clock
19
The Setting Method of a System Clock
20
Table 1.6 Example of Operating Frequency
20
Table 1.7 Operating Frequency Examples of High Speed and Middle Speed System Clocks
20
Low Speed Clock
22
ELOSC Setting (no Operation of External Low Speed Oscillator → Operation)
22
ELCLKIN Setting (no Operation of External Low Speed Oscillator → Operation)
22
Clock Supply Setting Function
23
Prescaler Clock
23
Table 1.8 Time Interval for Changing Prescaler Clocks
23
Operation Mode
24
Details of an Operation Mode
24
The Feature in each Mode
24
Transition to and Return from Low Power Consumption Mode
25
Selection of a Low Power Consumption Mode
25
Table 1.9 Low Power Consumption Mode Selection
25
The Peripheral Function State in a Low Power Consumption Mode
26
Table 1.10 Block Operation Status in each Low Power Consumption Mode
26
Switch to and Return from a Low Power Consumption Mode
28
IDLE Mode Transition Flow
28
Figure 1.2 Change State
28
STOP1 Mode Transition Flow
29
STOP2 Mode Transition Flow
30
Return from a Low Power Consumption Mode
31
The Release Source of a Low Power Consumption Mode
31
Table 1.11 Release Source List
31
Warming up at the Release of Low Power Consumption Mode
32
Table 1.12 Warming up
32
Restart Operation from STOP2 Mode
33
Figure 1.3 STOP2 Mode Restart Operation Flow
33
Clock Operation by Mode Transition
34
NORMAL → IDLE → NORMAL Operation Mode Transition
34
NORMAL → STOP1 → NORMAL Operation Mode Transition
34
Figure 1.4 NORMAL → STOP1 → NORMAL Operation Mode Transition
34
NORMAL → STOP2 → RESET → NORMAL Operation Mode Transition
35
Figure 1.5 NORMAL → STOP2 → RESET → NORMAL Operation Mode Transition
35
Explanation of a Register
36
Register List
36
Detail of Register
37
[CGPROTECT] (CG Write Protection Register)
37
[CGOSCCR] (Oscillation Control Register)
37
[CGSYSCR] (System Clock Control Register)
38
[CGSTBYCR] (Standby Control Register)
39
[CGPLL0SEL] (PLL Selection Register for Fsys)
39
[CGWUPHCR] (High Speed Oscillation Warming up Register)
40
[CGWUPLCR] (Low Speed Oscillation Warming up Register)
40
[CGFSYSMENC] (Middle Speed Clock Supply and Stop Register C for Fsysm)
41
[CGFSYSMENA] (Middle Speed Clock Supply and Stop Register a for Fsysm)
42
[CGFSYSMENB] (Middle Speed Clock Supply and Stop Register B for Fsysm)
44
[CGFSYSENA] (High Speed Clock Supply and Stop Register a for Fsysh)
46
[CGFCEN] (Clock Supply and Stop Register for Fc)
47
[CGSPCLKEN] (Clock Supply for ADC and Debug Circuit Register)
47
[CGEXTEND2] (Function Extension Register 2)
48
[RLMLOSCCR] (Low Speed Oscillation and Internal High Speed Oscillation 2 Clock Control Register)
48
[Rlmshtdnop](Power Supply Cut off Control Register)
49
[RLMPROTECT](RLM Write Protection Register)
49
Information According to Product
50
[Cgfsysena]
50
Table 1.13 [CGFSYSENA] Register Corresponding to each Product
50
[Cgfsysmena]
51
Table 1.14 [CGFSYSMENA] Register Corresponding to each Product
51
[Cgfsysenb]
52
Table 1.15 [CGFSYSMENB] Register Corresponding to each Product
52
[Cgfsysenc]
53
Table 1.16 [CGFSYSMENC] Register Corresponding to each Product
53
[Cgfcen]
54
Table 1.17 [CGFCEN] Register Corresponding to each Product
54
Memory Map
55
Outline
55
Tmpm4Gxf20
56
Figure 2.1 Tmpm4Gxf20
56
Tmpm4Gxf15
57
Figure 2.2 Tmpm4Gxf15
57
Tmpm4Gxf10
58
Figure 2.3 Tmpm4Gxf10
58
Tmpm4Gxfd
59
Figure 2.4 Tmpm4Gxfd
59
Bus Matrix
60
Structure
61
Single Chip Mode
61
Figure 2.5 Single Chip Mode
61
Single Boot Mode
62
Figure 2.6 Single Boot Mode
62
Connection Table
63
Code Area / SRAM Area / SMIF Area / External Bus Area
63
Table 2.1 Tmpm4Gxf20 Single Chip Mode
63
Table 2.2 Tmpm4Gxf20 Single Boot Mode
64
Table 2.3 Tmpm4Gxf15 Single Chip Mode
65
Table 2.4 Tmpm4Gxf15 Single Boot Mode
66
Table 2.5 Tmpm4Gxf10 Single Chip Mode
67
Table 2.6 Tmpm4Gxf10 Single Boot Mode
68
Table 2.7 Tmpm4Gxfd Single Chip Mode
69
Table 2.8 Tmpm4Gxfd Single Boot Mode
70
Peripheral Area
71
Table 2.9 Peripheral Area
71
RAM Access
72
Control Registers
72
Table 2.10 the Number of Clocks to Access each RAM
72
Reset and Power Control
74
Outline
74
Function and Operation
74
Cold Reset
74
Reset by a Power on Reset Circuit (Without Using a RESET_N Pin)
75
Figure 3.1 the Reset Operation by a Power on Reset Circuit
75
Reset by a RESET_N Pin
76
Figure 3.2 Reset Operation by a RESET_N Pin (1)
76
Figure 3.3 Reset Operation by a RESET_N Pin (2)
77
Reset Extension by LVD
78
Figure 3.4 the Reset Operation by LVD Reset
78
Warm Reset
79
Warm Reset by REST_N Pin
79
Warm Reset by Internal Reset
79
Figure 3.5 Warm Reset Operation
79
Reset by STOP2 Mode Release
80
Starting in Reset and Single Boot Mode
80
Start-Up by RESET_N Pin Signal
80
Figure 3.6 Starting in Power Supply Is on and Single Boot Mode
80
Start up by Power on Reset (Not Using RESET_N Pin Signal)
81
Figure 3.7 Starting Single Boot Mode Without Using Reset
81
Starting in the Single Boot Mode When Power Supply Is Stable
82
Figure 3.8 Starting in the Single Boot Mode When Power Supply Is Stable
82
Power on Reset Circuit
83
Operation at the Time of a Power on
83
Operation at the Time of Turn off
83
Figure 3.9 Power on Reset Circuit
83
Precautions When Turning off the Power
84
Figure 3.10 Falling Gradient When Turning off the Power
84
About Turn on Power Supply after Turn off
85
After Reset Release
85
A Reset Factor and the Reset Range
86
Table 3.1 a Reset Factor and the Range Initialized
86
Revision History
87
Table 4.1 Revision History
87
Restrictions on Product Use
88
Advertisement
Toshiba TXZ+ Series Reference Manual (64 pages)
2-bit RISC Microcontroller
Brand:
Toshiba
| Category:
Microcontrollers
| Size: 0.85 MB
Table of Contents
Table of Contents
2
Preface
6
Related Documents
6
Conventions
7
Terms and Abbreviations
9
Outlines
10
Clock Control
11
Clock Type
11
The Initial Value by a Reset Action
11
Clock System Diagram
12
Figure 1.1 Clock System Diagram
12
The Warming-Up Timer for a High Speed Oscillation
13
Warming-Up Function
13
A PLL Setup after Reset Release
14
Clock Multiplying Circuit (PLL) for Fsys
14
The Directions for a Warming-Up Timer
14
Table 1.1 Details of [CGPLL0SEL]<PLL0SET[23:0]> Setup
15
Table 1.2 PLL Correction (Example)
15
The Formula and the Example of a Setting of a PLL Multiplication Value
15
Change of the PLL Multiplication Value under Operation
16
Table 1.3 PLL0SET Setting Value (Example)
16
Fc Setup (Conduct PLL >>> PLL Stop)
17
Fc Setup (PLL Stop >>> PLL Start)
17
PLL Operation Start / Stop / Switching Procedure
17
System Clock
18
Table 1.4 Clock Domains of CPU and Peripherals
18
Table 1.5 Time Interval for Changing System Clock
18
Table 1.6 Example of Operating Frequency
18
Fosc Setup (Internal Oscillation >>> External Oscillation)
19
Table 1.7 Operating Frequency Examples of High Speed and Middle Speed System Clocks
19
The Setting Method of a System Clock
19
Fosc Setup (External Oscillation/External Clock Input >>> Internal Oscillation)
20
Fosc Setup (Internal Oscillation >>> External Clock Input)
20
Clock Supply Setting Function
21
Prescaler Clock
21
Table 1.8 Time Interval for Changing Prescaler Clocks
21
Operation Mode
22
Details of an Operation Mode
22
The Feature in each Mode
22
Selection of a Low Power Consumption Mode
23
Table 1.9 Low Power Consumption Mode Selection
23
Transition to and Return from Low Power Consumption Mode
23
Table 1.10 Block Operation Status in each Low Power Consumption Mode
24
The Peripheral Function State in a Low Power Consumption Mode
24
Figure 1.2 Mode State Transition
25
IDLE Mode Transition Flow
25
Mode State Transition
25
STOP1 Mode Transition Flow
26
Return from a Low Power Consumption Mode
27
Table 1.11 Release Source List
27
The Release Source of a Low Power Consumption Mode
27
Table 1.12 Warming-Up
28
Warming-Up at the Release of Low Power Consumption Mode
28
Clock Operation by Mode Transition
29
Figure 1.3 NORMAL >>> STOP1 >>> NORMAL Operation Mode Transition
29
NORMAL >>> IDLE >>> NORMAL Operation Mode Transition
29
NORMAL >>> STOP1 >>> NORMAL Operation Mode Transition
29
Explanation of Register
30
Register List
30
CGOSCCR] (Oscillation Control Register)
31
CGPROTECT] (CG Write Protection Register)
31
Detail of Register
31
CGSYSCR] (System Clock Control Register)
32
CGPLL0SEL] (PLL Selection Register for Fsys)
33
CGSTBYCR] (Standby Control Register)
33
CGFSYSMENA] (Supply and Stop Register a for Fsysm)
34
CGWUPHCR] (High Speed Oscillation Warming-Up Register)
34
CGFSYSMENB] (Supply and Stop Register B for Fsysm)
37
CGFSYSENA] (Supply and Stop Register a for Fsysh)
38
CGFCEN] (Clock Supply and Stop Register for Fc)
39
CGSPCLKEN] (Clock Supply and Stop Register for ADC and Debug Circuit)
39
Information According to Product
40
Cgfsysmena]
40
Table 1.13 [CGFSYSMENA] Register Corresponding to each Product
40
Cgfsysmenb]
41
Table 1.14 [CGFSYSMENB] Register Corresponding to each Product
41
Cgfcen]
42
Cgfsysena]
42
Table 1.15 [CGFSYSENA] Register Corresponding to each Product
42
Table 1.16 [CGFCEN] Register Corresponding to each Product
42
2 Memory Map
43
Outlines
43
Tmpm4Kxfya
44
Figure 2.1 Tmpm4Kxfya
44
Tmpm4Kxfwa
45
Figure 2.2 Tmpm4Kxfwa
45
Bus Matrix
46
Structure
47
Figure 2.3 Single Chip Mode
47
Single Chip Mode
47
Figure 2.4 Single Boot Mode
48
Single Boot Mode
48
Connection Table
49
Connection of Memory Related
49
Table 2.1 Single Chip Mode
49
Table 2.2 Single Boot Mode
49
Table 2.3 Single Chip Mode
50
Table 2.4 Single Boot Mode
50
Connection of Peripheral Function
51
Table 2.5 Connection of Peripheral Function
51
3 Reset and Power Supply Control
52
Outlines
52
Description of Function and Operation
52
Cold Reset
52
Figure 3.1 the Reset Operation by a Power on Reset Circuit
53
Reset by a Power on Reset Circuit (Without Using a RESET_N Pin)
53
Figure 3.2 Reset Operation by a RESET_N Pin (1)
54
Reset by a RESET_N Pin
54
Figure 3.3 Reset Operation by a RESET_N Pin (2)
55
Continuation of Reset by LVD
56
Figure 3.4 Reset Operation by LVD Reset
56
Warm Reset
57
Figure 3.5 Warm Reset Operation
57
Warm Reset by LVD
57
Warm Reset by Other Internal Reset
57
Warm Reset by RESET_N Pin
57
Starting in Single Boot Mode
58
Figure 3.6 When the Power Supply Is On, Starting in Single Boot Mode by the RESET_N Pin
58
Starting by the RESET_N Pin
58
Figure 3.7 Starting in the Single Boot Mode When Power Supply Is Stable
59
Starting in Single Boot Mode When Power Supply Is Stable
59
Power on Reset Circuit
60
Figure 3.8 Power on Reset Circuit
60
Operation at the Time of a Power Supply
60
Operation at the Time of Turn off
60
About Turn on Power Supply after Turn off
61
After Reset Release
61
Table 3.1 the Reset Factor and the Range Initialized
62
The Reset Factor and the Reset Range
62
4 Revision History
63
Table 4.1 Revision History
63
Restrictions on Product Use
64
Toshiba TXZ+ Series Reference Manual (72 pages)
Brand:
Toshiba
| Category:
Microcontrollers
| Size: 1.43 MB
Table of Contents
Table of Contents
2
Contents
2
List of Figures
5
List to Tables
5
Preface
6
Related Documents
6
Conventions
7
Terms and Abbreviations
9
Clock Control and Operation Mode
10
Outlines
10
Clock Control
11
Clock Type
11
The Initial Value by a Reset Operation
11
Clock System Diagram
12
Figure 1.1 Clock System Diagram
12
Warming up Function
13
The Warming up Timer for a High Speed Oscillation
13
The Warming up Timer for a Low Speed Oscillation
14
The Directions for Warming up Timer
14
Clock Multiplying Circuit (PLL) for Fsys
15
A PLL Setup after Reset Release
15
The Formula and the Example of a Setting of a PLL Multiplication Value
15
Change of the PLL Multiplication Value under Operation
17
PLL Operation Start/Stop/Switching Procedure
17
System Clock
18
The Setting Method of a System Clock
19
Clock Supply Setting Function
21
The Output Function of a Clock in the Terminal
21
Prescaler Clock
21
Operation Mode
22
Details of an Operation Mode
22
The Feature in each Mode
22
Low Power Consumption Mode
23
Selection of a Low Power Consumption Mode
23
The Peripheral Function State in a Low Power Consumption Mode
23
Mode State Transition
26
IDLE Mode Transition Flow
26
Figure 1.2 Mode State Transition
26
STOP1 Mode Transition Flow
27
STOP2 Mode Transition Flow
28
The Return Operation from a Low Power Consumption Mode
29
The Release Source of a Low Power Consumption Mode
29
Warming up at the Release of Low Power Consumption Mode
31
The Restart Operation from the STOP2 Mode
32
Figure 1.3 STOP2 Mode Restart Operation Flow
32
Clock Operation by Mode Transition
33
NORMAL → IDLE → NORMAL Operation Mode Transition
33
NORMAL → STOP1 → NORMAL Operation Mode Transition
33
Figure 1.4 NORMAL → STOP1 → NORMAL Operation Mode Transition
33
NORMAL → STOP2 → RESET → NORMAL Operation Mode Transition
34
Figure 1.5 NORMAL → STOP2 → RESET → NORMAL Operation Mode Transition
34
Explanation of Register
35
Register List
35
Clock and Mode Control
35
Low Speed Oscillation/Power Control (Note)
35
Register Description
36
CGPROTECT] (CG Write Protection Register)
36
CGOSCCR] (Oscillation Control Register)
36
CGSYSCR] (System Clock Control Register)
37
CGSTBYCR] (Standby Control Register)
38
CGSCOCR] (SCOUT Output Control Register)
38
CGPLL0SEL] (PLL Selection Register for Fsys)
39
CGWUPHCR] (High Speed Oscillation Warming up Register)
39
CGWUPLCR] (Low Speed Oscillation Warming up Register)
40
CGFSYSMENB] (Clock Supply and Stop Register B for Fsysm)
41
CGFSYSENA] (Clock Supply and Stop Register a for Fsys)
42
CGFSYSENB] (Clock Supply and Stop Register B for Fsys)
44
CGFCEN] (Clock Supply and Stop Register for Fc)
46
CGSPCLKEN] (Clock Supply and Stop Register for ADC and Debug Circuit)
46
RLMLOSCCR] (Low Speed Oscillation Control Register)
46
RLMSHTDNOP] (Power Supply Cut off Control Register)
46
RLMPROTECT] (RLM Write Protection Register)
47
Information According to Product
48
Cgfsysmenb]
48
Cgfsysena]
49
Cgfsysenb]
50
Memory Map
51
Overview
51
Tmpm3Hxfda
52
Figure 2.1 Tmpm3Hxfd
52
Tmpm3Hxfza
53
Figure 2.2 Tmpm3Hxfz
53
Tmpm3Hxfya
54
Figure 2.3 Tmpm3Hxfy
54
Bus Matrix
55
Structure
55
Single Chip Mode
55
Figure 2.4 Single Chip Mode
55
Single Boot Mode
56
Figure 2.5 Single Boot Mode
56
Connection Table
57
Code Area/ SRAM Area
57
Peripheral Area
58
Power Supply and Reset Operation
59
Outline
59
Function and Operation
60
Cold Reset
60
Reset by a Power on Reset Circuit (Without Using a RESET_N Pin)
61
Figure 3.1 the Reset Operation by a Power on Reset Circuit
61
Reset by a RESET_N Pin
62
Figure 3.2 Reset Operation by a RESET_N Pin (1)
62
Figure 3.3 Reset Operation by a RESET_N Pin (2)
63
Continuation of Reset by LVD
64
Figure 3.4 Reset Operation by LVD Reset
64
Warm Reset
65
Warm Reset by RESET_N Pin
65
Warm Reset by Internal Reset
65
Figure 3.5 Warm Reset Action
65
Reset by STOP2 Mode Release
66
Starting in Reset and Single Boot Mode
66
Figure 3.6 Starting in Power Supply Is on and Single Boot Mode
66
Figure 3.7 Starting in the Single Boot Mode When Power Supply Is Stable
67
Power on Reset Circuit
68
Operation at the Time of Turn on
68
Operation at the Time of Turn off
68
Figure 3.8 Power on Reset Circuit
68
Turning off and Re-Turning on Power Supply
69
When Using External Reset Circuit or Internal LVD Reset Output
69
When Not Using External Reset Circuit and Internal LVD Reset Output
69
After Reset Release
69
A Reset Factor and the Reset Initialized Range
70
Revision History
71
Restrictions on Product Use
72
Advertisement
Toshiba TXZ+ Series Reference Manual (52 pages)
Brand:
Toshiba
| Category:
Controller
| Size: 0.84 MB
Table of Contents
Table of Contents
2
Preface
5
Related Document
5
Conventions
6
Terms and Abbreviations
8
1 Outlines
9
2 Block Diagram
10
Figure 2.1 Block Diagram of CAN Controller
10
Table 2.1 List of Signals
10
3 Function and Operation
11
Clock Supply
11
CAN Interface
11
Function
12
Mailbox
12
Figure 3.1 Configuration of Mailboxes
12
Transmit Control Register
13
Receive Control Register
14
Figure 3.2 Timing When a Receive Message Lost Occurs
14
Remote Frame Control Register
15
Receive Filtering
16
Figure 3.3 Receive Filtering
16
Time Stamp Function
17
Figure 3.4 Timer Stamp Counter
17
Interrupt Control
18
Table 3.1 List of Interrupt Factors
18
Figure 3.5 Block Diagram of Canx Interrupt Signals
19
Operation Mode
20
Configuration Mode
20
Figure 3.6 Flowchart of Initial Setup of CAN Controller
21
Sleep Mode
22
Suspend Mode
22
Test Loop Back Mode
23
Test Error Mode
23
Figure 3.7 Flowchart of Setup of Test Loop Back Mode and Test Error Mode
23
Bit Configuration
24
Figure 3.8 CAN Bit Timing
24
Table 3.2 Restrictions When Setting the Baud Rate
25
4 Register
26
Register List
26
CAN Mailbox
27
Details of Registers
28
[Canxmbnid](Message ID Field Register)
28
[Canxmbntsvmcf](Time Stamp Values Message Control Field Register)
29
[Canxmbndl](Data Fields Register )
30
[Canxmbndh](Data Fields Register)
30
[Canxmc](Mailbox Configuration Register)
31
[Canxmd](Mailbox Direction Register)
31
[Canxtrs](Transmission Request Set Register)
32
[Canxtrr](Transmission Request Reset Register)
33
[Canxta](Transmission Acknowledge Register)
34
[Canxaa](Abort Acknowledge Register)
34
[Canxrmp](Receive Message Pending Register)
35
[Canxrml](Receive Message Lost Register)
36
Table 4.1 Change of [Canxrmp] and [Canxrml] Registers Before/ after a Message Is Received
36
[Canxlam](Local Acceptance Mask Register)
37
[Canxgam](Global Acceptance Mask Register)
38
[Canxmcr](Master Control Register)
39
[Canxgsr](Global Status Register)
40
[Canxbcr1](Bit Configuration Register1)
41
[Canxbcr2](Bit Configuration Register2)
41
[Canxgif](Global Interrupt Flag Register)
42
[Canxgim](Global Interrupt Mask Register)
43
[Canxmbtif](Mailbox Transmit Interrupt Flag Register)
44
[Canxmbrif](Mailbox Receive Interrupt Flag Register)
44
[Canxmbim](Mailbox Interrupt Mask Register)
44
[Canxcdr](Change Data Request Register)
45
[Canxrfp](Remote Frame Pending Register)
45
[Canxcec](Canx Error Counter Register)
46
[Canxtsp](Time Stamp Counter Prescaler Register)
47
[Canxtsc](Time Stamp Counter Register)
47
5 Usage
48
Receive Messages
48
Figure 5.1 Flowchart of Message Reception
48
Transmitting Message
49
Figure 5.2 Flowchart of Message Transmission
49
Remote Frame Handling
50
Figure 5.3 Flowchart of Remote Frame Handling Using the Automatic Reply Feature
50
6 Revision History
51
Table 6.1 Revision History
51
Restrictions on Product Use
52
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