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TOSHIBA TXZ SERIES Manuals
Manuals and User Guides for TOSHIBA TXZ SERIES. We have
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TOSHIBA TXZ SERIES manuals available for free PDF download: Reference Manual
Toshiba TXZ SERIES Reference Manual (67 pages)
32-bit RISC Microcontroller, Serial Peripheral Inteface TSPI-B
Brand:
Toshiba
| Category:
Microcontrollers
| Size: 1.59 MB
Table of Contents
Table of Contents
2
Preface
5
Related Document
5
Conventions
6
Terms and Abbreviation
8
Outline
9
Table 1.1 Functional Outline (SPI Mode, Master)
10
Table 1.2 Functional Outline (SPI Mode, Slave)
11
Table 1.3 Functional Outline (SIO Mode, Master)
12
Table 1.4 Functional Outline (SIO Mode, Slave)
13
Configuration
14
Figure 2.1 Block Diagram of TSPI
14
Table 2.1 List of Signals
15
Operation Description
16
Basic Operation
16
Clock Supply
16
Initial Setting of TSPI
16
Start and Stop Transfer
16
Data Format
17
Figure 3.1 Data Format
17
Data Format Without Parity
18
Figure 3.2 MSB First (32-Bit Data Without a Parity Bit)
18
Figure 3.3 MSB First (16-Bit Data Without a Parity Bit)
19
Figure 3.4 LSB First (32-Bit Data Without a Parity Bit)
20
Figure 3.5 LSB First (16-Bit Data Without a Parity Bit)
21
Data Format with a Parity
22
Figure 3.6 MSB First (31-Bit Data with a Parity)
22
Figure 3.7 MSB First (15-Bit Data with Parity)
23
Figure 3.8 LSB First (31-Bit Data with Parity)
24
Figure 3.9 LSB First (15-Bit Data with Parity)
25
Operation
26
Transfer Clock
26
Master Operation
26
Figure 3.10 Transfer Clock Generation Circuit
26
Slave Operation
27
Table 3.1 Example of F
27
Clk /Φt0/Φtx/ Transfer Clock and Usability
27
Communication Mode
28
SPI Mode
28
SIO Mode
29
Master / Slave Selection
29
Buffer Structure
29
Table 3.2 Data Format and Settable Fill Level
29
Data Length and FIFO Operation
30
Figure 3.11 Operation in 7 to 16-Bit Data Length
30
Figure 3.12 Operation in 17 to 32-Bit Data Length
31
Communication Operation Mode
32
Full Duplex Communication Mode
32
Figure 3.13 Operation Example of Full Duplex Communication
32
Transmit Mode
34
Figure 3.14 Operation Example of Transmit Mode
34
Receive Mode
35
Figure 3.15 Operation Example in Receive Mode
35
Transfer Mode
36
Single Transfer
36
Burst Transfer
36
Continuously Transfer
36
Data Sampling Timing
37
Table 3.3 Usability of Communication Mode and Data Sampling Timing
37
Table 3.4 Data Capture Timing
37
Figure 3.16 Data Sampling Timing of SPI Mode (Master)
38
Figure 3.17 Data Sampling Timing of SPI Mode (Slave)
39
Figure 3.18 Data Sampling Timing of SIO Mode (Master)
39
Figure 3.19 Data Sampling Timing of SIO Mode (Slave)
39
Special Control
40
Polarity of Tspixcs0/1/2/3 Signal and Generation Timing
40
Nd Edge Sampling)
40
Polarity of the Clock
41
Tspixtxd Output During Idle
41
Table 3.5 Tspixtxd Output During Idle State
41
Figure 3.21 Idle State in SPI Mode and the Transmit Pin Status
42
Figure 3.22 Idle State in SIO Mode and the Transmit Pin Status
42
Communication Control by Trigger
43
Figure 3.23 Circuit of Interrupt Request
44
Table 3.6 Interrupt Events and Requests
44
Error Interruption
45
Transmit Completion Interrupt/Receive Completion Interrupt
45
Transmit FIFO Interrupt/Receive FIFO Interrupt
45
Figure 3.24 Overrun Error and Underrun Error
46
Interrupt Request
44
Coordinated Movements by the Completion of Communication
47
DMA Request
47
Transmit DMA Request
47
Receive DMA Request
47
Software Reset
47
Registers
48
Register List
48
Detail of Register
49
Tspixcr0] (TSPI Control Register 0)
49
Table 4.1 Initialized Registers by Software Reset
49
Tspixcr1] (TSPI Control Register 1)
50
Tspixcr2] (TSPI Control Register 2)
52
Tspixcr3] (TSPI Control Register 3)
54
Tspixbr] (TSPI Baud Rate Register)
54
Tspixfmtr0] (TSPI Format Control Register 0)
55
Tspixfmtr1] (TSPI Format Control Register 1)
57
Tspixdr] (TSPI Data Register)
57
Tspixsr] (TSPI Status Register)
58
Table 4.2 the Timing of Write "0" to <TRXE>, and State of <TSPISUE
60
Table 4.3 Current Value of Fill Level Depending on the Range of <TLVL>/<RLVL
60
Tspixerr] (TSPI Error Flag Register)
61
Example for Use
62
Table 5.1 Transfer Starting and Stopping Operation in each Mode Setting (Master)
62
Precautions
64
Revision History
65
Table 7.1 Revision History
65
Restrictions on Product Use
67
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Toshiba TXZ SERIES Reference Manual (55 pages)
32-bit RISC Microcontroller Advanced Encoder Input Circuit (32-bit)
Brand:
Toshiba
| Category:
Microcontrollers
| Size: 0.67 MB
Table of Contents
Table of Contents
2
Preface
5
Related Documents
5
Conventions
6
Terms and Abbreviation
8
1 Outlines
9
2 Configuration
10
Figure 2.1 Block Diagram of Encoder Input Circuit
10
Table 1.1 Signal Input Pin
10
Table 2.1 List of Signals
10
3 Function and Operation
11
Clock Supply
11
Operation Mode
11
Table 3.1 Operation Modes
11
Encoder Mode
12
Figure 3.1 Encxz Input Is Valid ([Enxtncr]<Zen>=1)
12
Figure 3.2 Encxz Input Is Invalid ([Enxtncr]<Zen>=0)
13
Sensor Mode
15
Event Counter
15
Figure 3.3 3-Phase Decode ([Enxtncr]<P3En>=1)
15
Figure 3.4 2-Phase Decode ([Enxtncr]<P3En>=0)
16
Timer Count
17
Figure 3.5 3-Phase Decode ([Enxtncr]<P3En>=1)
17
Figure 3.6 2-Phase Decode ([Enxtncr]<P3En>=0)
17
Phase Count
19
Figure 3.7 3-Phase Decode ([Enxtncr]<P3En>=1)
19
Figure 3.8 2-Phase Decode ([Enxtncr]<P3En>=0)
19
Figure 3.10 Encxz Input Is Invalid ([Enxtncr]<Zen>=0)
21
Figure 3.9 Encxz Input Is Valid ([Enxtncr]<Zen>=1)
21
Timer Mode
21
Phase Counter Mode
23
Phase Measurement
23
Figure 3.11 Encxz Input Is Valid ([Enxtncr]<Zen>=1)
23
Figure 3.12 Encxz Input Is Invalid ([Enxtncr]<Zen>=0)
23
Phase Difference Measurement
25
Figure 3.13 Operation of Phase Counter Mode (Phase Difference)
25
Function Outline of each Circuit
26
Input Circuit
26
Figure 3.14 Input Circuit Configuration
26
Figure 3.15 PWM Synchronous Sampling
27
Sample Clock
27
Sampling Mode
27
Figure 3.16 Noise Cancellation (Continuous Sampling: <NCT>=3)
28
Figure 3.17 Noise Cancellation (PWM-On Interval Sampling and PWM-Off Interval Stop: <NCT>=4)
28
Noise Cancellation
28
Figure 3.18 Noise Cancellation (PWM-On Interval Sampling and PWM-Off Interval Clear: <NCT>=4)
29
Decoder
30
Figure 3.19 Decoder Circuit
30
Figure 3.20 2-Phase Decoder Waveform
31
Rotation Edge Detection and Direction Signal Generation
31
Figure 3.21 3-Phase Decoder Waveform
32
Z Judgment Circuit
32
Edge Detection Error Judgment
33
Skip Judgment and Abnormal Input Judgment
33
BEMF Detection Control
34
Buffer Update Control
34
Counter
35
Encoder Mode and Sensor Mode (Event Count)
35
Figure 3.22 Counter Circuit (Encoder Mode and Sensor Mode (Event Count))
35
Sensor Mode (Timer Count) and Timer Mode
36
Figure 3.23 Counter Configuration (Sensor Mode (Timer Count) and Timer Mode)
36
Sensor Mode (Phase Count) and Phase Counter Mode
37
Figure 3.24 Counter Configuration (Sensor Mode (Phase Count) and Phase Counter Mode)
37
Interrupt Control
38
Table 3.2 List of the Interrupt Factors
38
Table 3.3 List of Interrupt Factors in each Mode
38
4 Registers
39
List of Registers
39
Details of Registers
40
Enxtncr] (ENC Control Register)
40
Enxreload] (RELOAD Comparison Register)
44
Enxint] (INT Comparison Register)
44
Enxcnt] (Counter Register)
45
Enxmcmp] (MCMP Comparison Register)
45
Enxrate] (Phase Count Rate Register)
46
Enxsts] (Status Register)
47
Enxinpcr] (Input Procedure Control Register)
48
Enxsmpdly] (Sample Delay Register)
49
Enxinpmon] (Input Monitor Register)
49
Enxclkcr] (Sample Clock Control Register)
50
Enxintcr] (Interrupt Control Register)
51
Enxintf] (Interrupt Flag Register)
52
5 Precaution for Usage
53
6 Revision History
54
Table 6.1 Revision History
54
Restrictions on Product Use
55
Toshiba TXZ SERIES Reference Manual (54 pages)
32-bit RISC Microcontroller. CAN Controller (CAN-A)
Brand:
Toshiba
| Category:
Microcontrollers
| Size: 0.62 MB
Table of Contents
Table of Contents
2
Preface
5
Related Document
5
Conventions
6
Terms and Abbreviations
8
1 Outlines
9
2 Block Diagram
10
Figure 2.1 Block Diagram of CAN Controller
10
Table 2.1 List of Signals
10
3 Function and Operation
11
CAN Interface
11
Clock Supply
11
Function
12
Mailbox
12
Figure 3.1 Configuration of Mailboxes
12
Transmit Control Register
13
Receive Control Register
14
Figure 3.2 Timing When a Receive Message Lost Occurs
14
Remote Frame Control Register
15
Receive Filtering
16
Figure 3.3 Receive Filtering
16
Time Stamp Function
17
Figure 3.4 Timer Stamp Counter
17
Interrupt Control
18
Table 3.1 List of Interrupt Sources
18
Figure 3.5 Block Diagram of CAN Interrupt Signals
19
Operation Mode
20
Configuration Mode
20
Figure 3.6 Flowchart of Initial Setup of CAN Controller
21
Sleep Mode
22
Suspend Mode
22
Test Loop Back Mode
23
Test Error Mode
23
Figure 3.7 Flowchart of Setup of Test Loop Back Mode and Test Error Mode
24
Bit Configuration
25
Figure 3.8 CAN Bit Timing
25
Table 3.2 Restrictions When Setting the Baud Rate
26
4 Register
28
Register List
28
CAN Mailbox
29
Details of Registers
30
[Canmbnid]( Message ID Field Register)
30
[Canmbntsvmcf]( Time Stamp Values Message Control Field Register)
31
[Canmbndl](Data Fields Register )
32
[Canmbndh](Data Fields Register)
32
[Canmc](Mailbox Configuration Register)
33
[Canmd](Mailbox Direction Register)
33
[Cantrs](Transmission Request Set Register)
34
[Cantrr](Transmission Request Reset Register)
35
[Canta](Transmission Acknowledge Register)
36
[Canaa](Abort Acknowledge Register)
36
[Canrmp](Receive Message Pending Register)
37
[Canrml](Receive Message Lost Register)
38
Table 4.1 Change of [CANRMP] and [CANRML] Registers Before/ after a Message Is Received
38
[CANLAM]( Local Acceptance Mask Register)
39
[Cangam](Global Acceptance Mask Register)
40
[Canmcr](Master Control Register)
41
[Cangsr](Global Status Register)
42
[Canbcr1](Bit Configuration Register1)
43
[Canbcr2](Bit Configuration Register2)
43
[Cangif](Global Interrupt Flag Register)
44
[Cangim](Global Interrupt Mask Register)
45
[Canmbtif](Mailbox Transmit Interrupt Flag Register)
46
[Canmbrif](Mailbox Receive Interrupt Flag Register)
46
[Canmbim](Mailbox Interrupt Mask Register)
46
[Cancdr](Change Data Request Register)
47
[Canrfp](Remote Frame Pending Register)
47
[CANCEC](CAN Error Counter Register)
48
[Cantsp](Time Stamp Counter Prescaler Register)
49
[Cantsc](Time Stamp Counter Register)
49
5 Usage
50
Receive Messages
50
Figure 5.1 Flowchart of Message Reception
50
Transmitting Message
51
Figure 5.2 Flowchart of Message Transmission
51
Remote Frame Handling
52
Figure 5.3 Flowchart of Remote Frame Handling Using the Automatic Reply Feature
52
6 Revision History
53
Table 6.1 Revision History
53
Restrictions on Product Use
54
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TOSHIBA TXZ SERIES Reference Manual (20 pages)
Oscillation Frequency Detector
Brand:
TOSHIBA
| Category:
Microcontrollers
| Size: 0.39 MB
Table of Contents
Table of Contents
2
Preface
4
Related Document
4
Conventions
5
Terms and Abbreviations
7
1 Outlines
8
2 Configuration
9
Figure 2.1 Oscillation Frequency Detector Block Diagram
9
Table 2.1 List of Signals
9
3 Function and Operation
10
Setting Method
10
Detection Frequency
11
Figure 3.1 Example of Detection Frequency Range (in Case of 10Mhz)
11
Detection Start Timing
12
Detection
12
Table 3.1 Clock Examples
12
Available Operation Mode of MCU
13
External High Speed Oscillation Clock Detection
13
4 Registers
14
List of Registers
14
OFDCR1] (Frequency Detection Control Register 1)
15
OFDMON] (Detection Target Clock 1 Monitor Setting Register)
15
OFDMN0] (Minimum Detection Frequency Setting Register 0 (EHOSC))
15
OFDMN1] (Minimum Detection Frequency Setting Register 1 (Fc))
15
OFDMX0] (Maximum Detection Frequency Setting Register 0 (EHOSC))
16
OFDMX1] (Maximum Detection Frequency Setting Register 1 (Fc))
16
OFDRST] (Reset Control Register)
16
OFDCR2] (Frequency Detection Control Register 2)
16
OFDSTAT] (Status Register)
17
5 Usage Example
18
Figure 5.1 Example of Operational Procedure
18
6 Revision History
19
Table 6.1 Revision History
19
Restrictions on Product Use
20
Toshiba TXZ SERIES Reference Manual (17 pages)
32-bit RISC Microcontroller
Brand:
Toshiba
| Category:
Microcontrollers
| Size: 0.32 MB
Table of Contents
Table of Contents
2
Preface
4
Related Document
4
Conventions
5
Terms and Abbreviations
7
1 Outline
8
2 Configuration
9
Figure 2.1 Configuration Diagram of OPAMP Module
9
Table 2.1 List of Signals
9
3 Operation Description
10
Clock Supply
10
Voltage Input
10
OPAMP Function Control
10
Gain Control
10
Voltage Output
10
Connection Diagram of OPAMP
11
Figure 3.1 Connection Diagram of OPAMP
11
4 Registers
12
Register List
12
Detail of Registers
12
AMPCTLA] (OPAMP Control Register A)
12
5 Usage
13
Example of Use During Motor Control (Shunt Resistor Voltage Measurement Operation)
13
Figure 5.1 Assumed Circuit at Motor Control Operation
13
Table 5.1 Relationship between Gain Setting and Amplifier Output During Motor Control Operation
14
Usage Examples for Single Amplifier Operation
15
Figure 5.2 Gain Setting Circuit for Single Amplifier Operation
15
Table 5.2 Relationship between Gain Setting and Amplifier Output When Single Amplifier Operation
15
6 Revision History
16
Table 6.1 Revision History
16
Restrictions on Product Use
17
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