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Toshiba TMPM4K manuals available for free PDF download: Reference Manual
Toshiba TMPM4K Reference Manual (89 pages)
32-bit RISC
Brand:
Toshiba
| Category:
Microcontrollers
| Size: 3.76 MB
Table of Contents
Table of Contents
2
Preface
7
Related Documents
7
Conventions
8
Terms and Abbreviations
10
Overview
11
Information of Peripheral Function
11
Register Base Address
11
Table 2.1 Type of Register Base Address
11
Trigger Selector(TRGSEL)
12
Figure 2.1 Example of Trigger Selector Connection
12
Trigger Selector List for the each Products
13
Table 2.2 Trigger Selector List for each Product (1/5)
13
Table 2.3 Trigger Selector List for each Product (2/5)
14
Table 2.4 Trigger Selector List for each Product (3/5)
15
Table 2.5 Trigger Selector List for each Product (4/5)
16
Table 2.6 Trigger Selector List for each Product (5/5)
17
Operation and Setting
18
List of Registers
19
Details of Registers
20
Tselxcr0] (Control Register 0)
20
Tselxcr1] (Control Register1)
22
Tselxcr2] (Control Register 2)
24
Tselxcr3] (Control Register 3)
26
Tselxcr4] (Control Register 4)
28
Tselxcr5] (Control Register 5)
30
Tselxcr6] (Control Register 6)
32
Tselxcr7] (Control Register 7)
34
Tselxcr8] (Control Register 8)
36
Tselxcr9] (Control Register 9)
38
Tselxcr10] (Control Register 10)
40
Direct Memory Access Controller
41
Built-In Unit
41
DMA Request Table
41
Table 2.7 DMAC Built-In Unit
41
Table 2.8 DMA Request Table (1/4)
41
Table 2.9 DMA Request Table (2/4)
42
Table 2.10 DMA Request Table (3/4)
43
Table 2.11 DMA Request List (4/4)
44
32-Bit Timer Event Counter(T32A)
45
Built-In Channel
45
Table 2.12 T32A Built-In Channel
45
Functional Pins
46
Table 2.13 T32A Functional Pin and Port (1/2)
46
Table 2.14 T32A Functional Pins and Port (2/2)
47
Clock for Prescaler
48
Internal Signal Connection Specification
48
Capture Trigger Signal Connection
48
Table 2.15 T32A Clock for Prescaler
48
Table 2.16 T32A Capture Trigger Connection (1/3)
49
Table 2.17 T32A Capture Trigger Connection (2/3)
50
Table 2.18 T32A Capture Trigger Connection (3/3)
51
Synchronous Control Connection
52
Table 2.19 T32A Synchronous Control Connection Specifications
52
Pulse Counter List for each Product
53
Table 2.20 T32A Pulse Counter List for each Product
53
DMA Request
54
Table 2.21 T32A DMA Request (1/2)
54
Internal Signal Connection Specification
55
Table 2.22 T32A DMA Request (2/2)
55
Universal Asynchronous Receiver Transmitter Circuit(UART)
56
Built-In Channel
56
Function Pin and Port
56
Table 2.23 UART Built-In Channel
56
Table 2.24 UART Functional Pin and Port
56
Half Clock Mode Support
57
Clock for Prescaler
57
DMA Request
57
Table 2.25 UART Clock for Prescaler
57
Table 2.26 UART DMA Request
57
Internal Signal Connection Specification
58
Trigger Transfer Signal Connection
58
Table 2.27 UART Trigger Transfer Signal Connection
58
T32A Connection
59
Table 2.28 UART Inside Connection List: Output
59
Serial Peripheral Interface(TSPI)
60
Built-In Channel
60
Function Pin and Port
60
Table 2.29 TSPI Built-In Channel
60
Table 2.30 TSPI Function Functional Pin and Port
60
Transfer Mode of each Product
61
Tspixcr2]<Rxdly> Set Value
61
Clock for Prescaler
61
Table 2.31 TSPI Mode List
61
Table 2.32 TSPI [Tspixcr2]<Rxdly> Set Value
61
Table 2.33 TSPI Clock for Prescaler
61
Internal Signal Connection Specification
62
Trigger Transfer Signal Connection
62
Table 2.34 TSPI Trigger Transfer
62
T32A Connection
63
DMA Request
63
Table 2.35 TSPI Inside Connection (Output)
63
Table 2.36 TSPI DMA Request
63
I 2 C Interface
64
Built-In Channel
64
Function Pin and Port
64
Clock for Prescaler
64
Table 2.37 I 2 C Interface Built-In Channel
64
Table 2.38 I C Interface Function Pin and Port
64
Table 2.39 I 2 C Interface Clock for Prescaler
64
DMA Request
65
Table 2.40 I 2 C Interface DMA Request
65
12-Bit Analog to Digital Converter(ADC)
66
Built-In Unit
66
Function Pin and Port
66
Table 2.41 ADC Built-In Unit
66
Table 2.42 ADC Function Pin and Port
66
Conversion Clock of ADC
67
Startup Trigger
67
Table 2.43 Conversion Clock of ADC
67
Table 2.44 ADC Startup Trigger
67
DMA Request
68
Other Connection
68
Table 2.45 ADC DMA Request
68
Table 2.46 ADC Inside Connection: Output
68
Advanced Programmable Motor Control Circuit(A-PMD)
69
Built-In Channel
69
Function Pin and Port
69
Table 2.47 A-PMD Built-In Channel
69
Table 2.48 A-PMD Function Pin
69
DMA Request
70
Table 2.49 A-PMD DMA Request
70
Internal Signal Connection Specification
71
Other Connection
71
Table 2.50 A-PMD Inside Connection List: Input
71
Inter-Channel Synchronous Control Connection
72
Table 2.51 A-PMD Inside Connection List: Output
72
Table 2.52 PMD Inter-Channel Synchronous Control Connection
72
Advanced Vector Engine Plus(A-VE+)
73
Built-In Channel
73
Other Connection
73
Table 2.53 A-VE+ Built-In Channel
73
Table 2.54 A-VE+ Internal Connection Specification: Input
73
Table 2.55 A-VE+ Internal Connection Specification: Output
73
Advanced Encoder Input Circuit(A-ENC)
74
Built-In Channel
74
Function Pin and Port
74
Table 2.56 A-ENC Built-In Channel
74
Table 2.57 A-ENC Function Pin
74
Internal Signal Connection Specification
75
T32A/A-PMD Connection
75
Table 2.58 A-ENC Internal Connection Specification: Input
75
Table 2.59 A-ENC Internal Connection Specification: Output
75
Operational Amplifier (OPAMP)
76
Built-In Unit
76
Connected Pin
76
Internal Connection
76
Table 2.60 OPAMP Built-In Unitl
76
Table 2.61 OPAMP Connected Pin
76
Table 2.62 OPAMP Internal Connection
76
Clock Selective Watchdog Timer(SIWDT)
77
Built-In Channel
77
Count Clock
77
Output Control
77
Table 2.63 SIWDT Built-In Channel
77
Table 2.64 SIWDT Count Clock
77
Table 2.65 SIWDT Output Control
77
CRC Calculation Circuit(CRC)
78
RAM Parity(RAMP)
78
Built-In Channel
78
Error Detection Block Area
78
Table 2.66 CRC Built-In Channel
78
Table 2.67 RAMP Built-In Channel
78
Table 2.68 RAM Area and Address of RAMP
78
Oscillation Frequency Detection Circuit(OFD)
79
Support Products
79
Reference Clock
79
Clock for Detection
79
Table 2.69 OFD Support Product
79
Table 2.70 OFD Reference Clock
79
Table 2.71 OFD Clock for Detection
79
Debug Interface
80
Debug Interface List for each Product
80
Table 2.72 Debug Interface List
80
Non Break Debug Interface (NBDIF)
81
Correspondence Table
81
NBDIF List for each Product
81
Table 2.73 NBDIF Correspondence Table
81
Table 2.74 NBDIF Interface List
81
Digital Noise Filter(DNF)
82
Built-In Unit
82
External Interrupt List for the each Product
82
Table 2.75 DNF Built-In Unit
82
Table 2.76 External Interrupt and DNF
82
Sampling Source Clock
83
Trimming Circuit(TRM)
83
Support Products
83
Target Oscillator
83
Table 2.77 DNF Sampling Source Clock
83
Table 2.78 TRM Support Product
83
Table 2.79 TRM Trimming Target Oscillator
83
Voltage Detection Circuit(LVD)
84
Support Products
84
Detection Power Supply
84
Table 2.80 LVD Support Product
84
Table 2.81 LVD Detection Power Supply
84
Flash Memory
85
Clock for the Programming/Erasing
85
The Code Flash Block Configuration of each Product
85
Table 2.82 Clock for Programming/Erasing
85
Table 2.83 the Code Flash of each Product
85
Single Boot Resource
86
Table 2.84 Single Boot Resource
86
Revision History
87
Table 3.1 Revision History
87
Restrictions on Product Use
89
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Toshiba TMPM4K Reference Manual (68 pages)
32-bit RISC Microcontroller
Brand:
Toshiba
| Category:
Microcontrollers
| Size: 0.91 MB
Table of Contents
Table of Contents
2
Preface
6
Related Documents
6
Conventions
7
Terms and Abbreviations
9
1 Clock Control and Operation Mode
10
Outlines
10
Clock Control
11
Clock Type
11
The Initial Value by a Reset Action
11
Clock System Diagram
12
Figure 1.1 Clock System Diagram
12
Warming-Up Function
13
The Warming-Up Timer for a High Speed Oscillation
13
The Directions for a Warming-Up Timer
14
Clock Multiplying Circuit (PLL) for Fsys
14
A PLL Setup after Reset Release
14
Table 1.1 Details of [CGPLL0SEL]<PLL0SET[23:0]> Setup
15
Table 1.2 PLL Correction (Example)
15
The Formula and the Example of a Setting of a PLL Multiplication Value
15
Change of the PLL Multiplication Value under Operation
16
Table 1.3 PLL0SET Setting Value (Example)
16
Fc Setup (Conduct PLL >>> PLL Stop)
17
Fc Setup (PLL Stop >>> PLL Start)
17
PLL Operation Start / Stop / Switching Procedure
17
System Clock
18
Table 1.4 Clock Domains of CPU and Peripherals
18
Table 1.5 Time Interval for Changing System Clock
18
Table 1.6 Example of Operating Frequency
18
Fosc Setup (Internal Oscillation >>> External Oscillation)
19
Table 1.7 Operating Frequency Examples of High Speed and Middle Speed System Clocks
19
The Setting Method of a System Clock
19
Fosc Setup (External Oscillation/External Clock Input >>> Internal Oscillation)
20
Fosc Setup (Internal Oscillation >>> External Clock Input)
20
Clock Supply Setting Function
21
Prescaler Clock
21
Table 1.8 Time Interval for Changing Prescaler Clocks
21
Operation Mode
22
Details of an Operation Mode
22
The Feature in each Mode
22
Selection of a Low Power Consumption Mode
23
Table 1.9 Low Power Consumption Mode Selection
23
Transition to and Return from Low Power Consumption Mode
23
Table 1.10 Block Operation Status in each Low Power Consumption Mode
24
The Peripheral Function State in a Low Power Consumption Mode
24
Mode State Transition
25
Figure 1.2 Mode State Transition
25
IDLE Mode Transition Flow
25
STOP1 Mode Transition Flow
26
Return from a Low Power Consumption Mode
27
Table 1.11 Release Source List
27
The Release Source of a Low Power Consumption Mode
27
Table 1.12 Warming-Up
28
Warming-Up at the Release of Low Power Consumption Mode
28
Clock Operation by Mode Transition
29
Figure 1.3 NORMAL >>> STOP1 >>> NORMAL Operation Mode Transition
29
NORMAL >>> IDLE >>> NORMAL Operation Mode Transition
29
NORMAL >>> STOP1 >>> NORMAL Operation Mode Transition
29
Explanation of Register
30
Register List
30
Detail of Register
31
CGOSCCR] (Oscillation Control Register)
31
CGPROTECT] (CG Write Protection Register)
31
CGSYSCR] (System Clock Control Register)
32
CGPLL0SEL] (PLL Selection Register for Fsys)
33
CGSTBYCR] (Standby Control Register)
33
CGFSYSMENA] (Supply and Stop Register a for Fsysm)
34
CGWUPHCR] (High Speed Oscillation Warming-Up Register)
34
CGFSYSMENB] (Supply and Stop Register B for Fsysm)
37
CGFSYSENA] (Supply and Stop Register a for Fsysh)
38
CGFCEN] (Clock Supply and Stop Register for Fc)
39
CGSPCLKEN] (Clock Supply and Stop Register for ADC and Debug Circuit)
39
Information According to Product
40
Cgfsysmena]
40
Table 1.13 [CGFSYSMENA] Register Corresponding to each Product
40
Cgfsysmenb]
41
Table 1.14 [CGFSYSMENB] Register Corresponding to each Product
41
Cgfsysena]
42
Cgfcen]
42
Table 1.15 [CGFSYSENA] Register Corresponding to each Product
42
Table 1.16 [CGFCEN] Register Corresponding to each Product
42
2 Memory Map
43
Outlines
43
Tmpm4Kxf10A
44
Figure 2.1 Tmpm4Kxf10A
44
Tmpm4Kxfda
45
Figure 2.2 Tmpm4Kxfda
45
Tmpm4Kxfya
46
Figure 2.3 Tmpm4Kxfya
46
Tmpm4Kxfwa
47
Figure 2.4 Tmpm4Kxfwa
47
Bus Matrix
48
Structure
49
Figure 2.5 Single Chip Mode
49
Single Chip Mode
49
Figure 2.6 Single Boot Mode
50
Single Boot Mode
50
Connection Table
51
Connection of Memory Related
51
Table 2.1 Single Chip Mode
51
Table 2.2 Single Boot Mode
51
Table 2.3 Single Chip Mode
52
Table 2.4 Single Boot Mode
52
Table 2.5 Single Chip Mode
53
Table 2.6 Single Boot Mode
53
Table 2.7 Single Chip Mode
54
Table 2.8 Single Boot Mode
54
Connection of Peripheral Function
55
Table 2.9 Connection of Peripheral Function
55
3 Reset and Power Supply Control
56
Outlines
56
Description of Function and Operation
56
Cold Reset
56
Figure 3.1 the Reset Operation by a Power on Reset Circuit
57
Reset by a Power on Reset Circuit (Without Using a RESET_N Pin)
57
Figure 3.2 Reset Operation by a RESET_N Pin (1)
58
Reset by a RESET_N Pin
58
Figure 3.3 Reset Operation by a RESET_N Pin (2)
59
Continuation of Reset by LVD
60
Figure 3.4 Reset Operation by LVD Reset
60
Warm Reset
61
Figure 3.5 Warm Reset Operation
61
Warm Reset by LVD
61
Warm Reset by Other Internal Reset
61
Warm Reset by RESET_N Pin
61
Starting in Single Boot Mode
62
Figure 3.6 When the Power Supply Is On, Starting in Single Boot Mode by the RESET_N Pin
62
Starting by the RESET_N Pin
62
Figure 3.7 Starting in the Single Boot Mode When Power Supply Is Stable
63
Starting in Single Boot Mode When Power Supply Is Stable
63
Power on Reset Circuit
64
Figure 3.8 Power on Reset Circuit
64
Operation at the Time of a Power Supply
64
Operation at the Time of Turn off
64
Turning off and Re-Turning on Power Supply
65
When Not Using External Reset Circuit and Internal LVD Reset Output
65
When Using External Reset Circuit or Internal LVD Reset Output
65
After Reset Release
65
Table 3.1 the Reset Factor and the Range Initialized
66
The Reset Factor and the Reset Range
66
4 Revision History
67
Table 4.1 Revision History
67
Restrictions on Product Use
68
Toshiba TMPM4K Reference Manual (64 pages)
2-bit RISC Microcontroller
Brand:
Toshiba
| Category:
Microcontrollers
| Size: 0.85 MB
Table of Contents
Table of Contents
2
Preface
6
Related Documents
6
Conventions
7
Terms and Abbreviations
9
Outlines
10
Clock Control
11
Clock Type
11
The Initial Value by a Reset Action
11
Clock System Diagram
12
Figure 1.1 Clock System Diagram
12
The Warming-Up Timer for a High Speed Oscillation
13
Warming-Up Function
13
A PLL Setup after Reset Release
14
Clock Multiplying Circuit (PLL) for Fsys
14
The Directions for a Warming-Up Timer
14
Table 1.1 Details of [CGPLL0SEL]<PLL0SET[23:0]> Setup
15
Table 1.2 PLL Correction (Example)
15
The Formula and the Example of a Setting of a PLL Multiplication Value
15
Change of the PLL Multiplication Value under Operation
16
Table 1.3 PLL0SET Setting Value (Example)
16
Fc Setup (Conduct PLL >>> PLL Stop)
17
Fc Setup (PLL Stop >>> PLL Start)
17
PLL Operation Start / Stop / Switching Procedure
17
System Clock
18
Table 1.4 Clock Domains of CPU and Peripherals
18
Table 1.5 Time Interval for Changing System Clock
18
Table 1.6 Example of Operating Frequency
18
Fosc Setup (Internal Oscillation >>> External Oscillation)
19
Table 1.7 Operating Frequency Examples of High Speed and Middle Speed System Clocks
19
The Setting Method of a System Clock
19
Fosc Setup (External Oscillation/External Clock Input >>> Internal Oscillation)
20
Fosc Setup (Internal Oscillation >>> External Clock Input)
20
Clock Supply Setting Function
21
Prescaler Clock
21
Table 1.8 Time Interval for Changing Prescaler Clocks
21
Operation Mode
22
Details of an Operation Mode
22
The Feature in each Mode
22
Selection of a Low Power Consumption Mode
23
Table 1.9 Low Power Consumption Mode Selection
23
Transition to and Return from Low Power Consumption Mode
23
Table 1.10 Block Operation Status in each Low Power Consumption Mode
24
The Peripheral Function State in a Low Power Consumption Mode
24
Figure 1.2 Mode State Transition
25
IDLE Mode Transition Flow
25
Mode State Transition
25
STOP1 Mode Transition Flow
26
Return from a Low Power Consumption Mode
27
Table 1.11 Release Source List
27
The Release Source of a Low Power Consumption Mode
27
Table 1.12 Warming-Up
28
Warming-Up at the Release of Low Power Consumption Mode
28
Clock Operation by Mode Transition
29
Figure 1.3 NORMAL >>> STOP1 >>> NORMAL Operation Mode Transition
29
NORMAL >>> IDLE >>> NORMAL Operation Mode Transition
29
NORMAL >>> STOP1 >>> NORMAL Operation Mode Transition
29
Explanation of Register
30
Register List
30
CGOSCCR] (Oscillation Control Register)
31
CGPROTECT] (CG Write Protection Register)
31
Detail of Register
31
CGSYSCR] (System Clock Control Register)
32
CGPLL0SEL] (PLL Selection Register for Fsys)
33
CGSTBYCR] (Standby Control Register)
33
CGFSYSMENA] (Supply and Stop Register a for Fsysm)
34
CGWUPHCR] (High Speed Oscillation Warming-Up Register)
34
CGFSYSMENB] (Supply and Stop Register B for Fsysm)
37
CGFSYSENA] (Supply and Stop Register a for Fsysh)
38
CGFCEN] (Clock Supply and Stop Register for Fc)
39
CGSPCLKEN] (Clock Supply and Stop Register for ADC and Debug Circuit)
39
Information According to Product
40
Cgfsysmena]
40
Table 1.13 [CGFSYSMENA] Register Corresponding to each Product
40
Cgfsysmenb]
41
Table 1.14 [CGFSYSMENB] Register Corresponding to each Product
41
Cgfcen]
42
Cgfsysena]
42
Table 1.15 [CGFSYSENA] Register Corresponding to each Product
42
Table 1.16 [CGFCEN] Register Corresponding to each Product
42
2 Memory Map
43
Outlines
43
Tmpm4Kxfya
44
Figure 2.1 Tmpm4Kxfya
44
Tmpm4Kxfwa
45
Figure 2.2 Tmpm4Kxfwa
45
Bus Matrix
46
Structure
47
Figure 2.3 Single Chip Mode
47
Single Chip Mode
47
Figure 2.4 Single Boot Mode
48
Single Boot Mode
48
Connection Table
49
Connection of Memory Related
49
Table 2.1 Single Chip Mode
49
Table 2.2 Single Boot Mode
49
Table 2.3 Single Chip Mode
50
Table 2.4 Single Boot Mode
50
Connection of Peripheral Function
51
Table 2.5 Connection of Peripheral Function
51
3 Reset and Power Supply Control
52
Outlines
52
Description of Function and Operation
52
Cold Reset
52
Figure 3.1 the Reset Operation by a Power on Reset Circuit
53
Reset by a Power on Reset Circuit (Without Using a RESET_N Pin)
53
Figure 3.2 Reset Operation by a RESET_N Pin (1)
54
Reset by a RESET_N Pin
54
Figure 3.3 Reset Operation by a RESET_N Pin (2)
55
Continuation of Reset by LVD
56
Figure 3.4 Reset Operation by LVD Reset
56
Warm Reset
57
Figure 3.5 Warm Reset Operation
57
Warm Reset by LVD
57
Warm Reset by Other Internal Reset
57
Warm Reset by RESET_N Pin
57
Starting in Single Boot Mode
58
Figure 3.6 When the Power Supply Is On, Starting in Single Boot Mode by the RESET_N Pin
58
Starting by the RESET_N Pin
58
Figure 3.7 Starting in the Single Boot Mode When Power Supply Is Stable
59
Starting in Single Boot Mode When Power Supply Is Stable
59
Power on Reset Circuit
60
Figure 3.8 Power on Reset Circuit
60
Operation at the Time of a Power Supply
60
Operation at the Time of Turn off
60
About Turn on Power Supply after Turn off
61
After Reset Release
61
Table 3.1 the Reset Factor and the Range Initialized
62
The Reset Factor and the Reset Range
62
4 Revision History
63
Table 4.1 Revision History
63
Restrictions on Product Use
64
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