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TXZ+ TMPM4KLF10AUG
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Manuals and User Guides for Toshiba TXZ+ TMPM4KLF10AUG. We have
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Toshiba TXZ+ TMPM4KLF10AUG manual available for free PDF download: Reference Manual
Toshiba TXZ+ TMPM4KLF10AUG Reference Manual (68 pages)
32-bit RISC Microcontroller
Brand:
Toshiba
| Category:
Microcontrollers
| Size: 0.91 MB
Table of Contents
Table of Contents
2
Preface
6
Related Documents
6
Conventions
7
Terms and Abbreviations
9
1 Clock Control and Operation Mode
10
Outlines
10
Clock Control
11
Clock Type
11
The Initial Value by a Reset Action
11
Clock System Diagram
12
Figure 1.1 Clock System Diagram
12
Warming-Up Function
13
The Warming-Up Timer for a High Speed Oscillation
13
The Directions for a Warming-Up Timer
14
Clock Multiplying Circuit (PLL) for Fsys
14
A PLL Setup after Reset Release
14
Table 1.1 Details of [CGPLL0SEL]<PLL0SET[23:0]> Setup
15
Table 1.2 PLL Correction (Example)
15
The Formula and the Example of a Setting of a PLL Multiplication Value
15
Change of the PLL Multiplication Value under Operation
16
Table 1.3 PLL0SET Setting Value (Example)
16
Fc Setup (Conduct PLL >>> PLL Stop)
17
Fc Setup (PLL Stop >>> PLL Start)
17
PLL Operation Start / Stop / Switching Procedure
17
System Clock
18
Table 1.4 Clock Domains of CPU and Peripherals
18
Table 1.5 Time Interval for Changing System Clock
18
Table 1.6 Example of Operating Frequency
18
Fosc Setup (Internal Oscillation >>> External Oscillation)
19
Table 1.7 Operating Frequency Examples of High Speed and Middle Speed System Clocks
19
The Setting Method of a System Clock
19
Fosc Setup (External Oscillation/External Clock Input >>> Internal Oscillation)
20
Fosc Setup (Internal Oscillation >>> External Clock Input)
20
Clock Supply Setting Function
21
Prescaler Clock
21
Table 1.8 Time Interval for Changing Prescaler Clocks
21
Operation Mode
22
Details of an Operation Mode
22
The Feature in each Mode
22
Selection of a Low Power Consumption Mode
23
Table 1.9 Low Power Consumption Mode Selection
23
Transition to and Return from Low Power Consumption Mode
23
Table 1.10 Block Operation Status in each Low Power Consumption Mode
24
The Peripheral Function State in a Low Power Consumption Mode
24
Mode State Transition
25
Figure 1.2 Mode State Transition
25
IDLE Mode Transition Flow
25
STOP1 Mode Transition Flow
26
Return from a Low Power Consumption Mode
27
Table 1.11 Release Source List
27
The Release Source of a Low Power Consumption Mode
27
Table 1.12 Warming-Up
28
Warming-Up at the Release of Low Power Consumption Mode
28
Clock Operation by Mode Transition
29
Figure 1.3 NORMAL >>> STOP1 >>> NORMAL Operation Mode Transition
29
NORMAL >>> IDLE >>> NORMAL Operation Mode Transition
29
NORMAL >>> STOP1 >>> NORMAL Operation Mode Transition
29
Explanation of Register
30
Register List
30
Detail of Register
31
CGOSCCR] (Oscillation Control Register)
31
CGPROTECT] (CG Write Protection Register)
31
CGSYSCR] (System Clock Control Register)
32
CGPLL0SEL] (PLL Selection Register for Fsys)
33
CGSTBYCR] (Standby Control Register)
33
CGFSYSMENA] (Supply and Stop Register a for Fsysm)
34
CGWUPHCR] (High Speed Oscillation Warming-Up Register)
34
CGFSYSMENB] (Supply and Stop Register B for Fsysm)
37
CGFSYSENA] (Supply and Stop Register a for Fsysh)
38
CGFCEN] (Clock Supply and Stop Register for Fc)
39
CGSPCLKEN] (Clock Supply and Stop Register for ADC and Debug Circuit)
39
Information According to Product
40
Cgfsysmena]
40
Table 1.13 [CGFSYSMENA] Register Corresponding to each Product
40
Cgfsysmenb]
41
Table 1.14 [CGFSYSMENB] Register Corresponding to each Product
41
Cgfsysena]
42
Cgfcen]
42
Table 1.15 [CGFSYSENA] Register Corresponding to each Product
42
Table 1.16 [CGFCEN] Register Corresponding to each Product
42
2 Memory Map
43
Outlines
43
Tmpm4Kxf10A
44
Figure 2.1 Tmpm4Kxf10A
44
Tmpm4Kxfda
45
Figure 2.2 Tmpm4Kxfda
45
Tmpm4Kxfya
46
Figure 2.3 Tmpm4Kxfya
46
Tmpm4Kxfwa
47
Figure 2.4 Tmpm4Kxfwa
47
Bus Matrix
48
Structure
49
Figure 2.5 Single Chip Mode
49
Single Chip Mode
49
Figure 2.6 Single Boot Mode
50
Single Boot Mode
50
Connection Table
51
Connection of Memory Related
51
Table 2.1 Single Chip Mode
51
Table 2.2 Single Boot Mode
51
Table 2.3 Single Chip Mode
52
Table 2.4 Single Boot Mode
52
Table 2.5 Single Chip Mode
53
Table 2.6 Single Boot Mode
53
Table 2.7 Single Chip Mode
54
Table 2.8 Single Boot Mode
54
Connection of Peripheral Function
55
Table 2.9 Connection of Peripheral Function
55
3 Reset and Power Supply Control
56
Outlines
56
Description of Function and Operation
56
Cold Reset
56
Figure 3.1 the Reset Operation by a Power on Reset Circuit
57
Reset by a Power on Reset Circuit (Without Using a RESET_N Pin)
57
Figure 3.2 Reset Operation by a RESET_N Pin (1)
58
Reset by a RESET_N Pin
58
Figure 3.3 Reset Operation by a RESET_N Pin (2)
59
Continuation of Reset by LVD
60
Figure 3.4 Reset Operation by LVD Reset
60
Warm Reset
61
Figure 3.5 Warm Reset Operation
61
Warm Reset by LVD
61
Warm Reset by Other Internal Reset
61
Warm Reset by RESET_N Pin
61
Starting in Single Boot Mode
62
Figure 3.6 When the Power Supply Is On, Starting in Single Boot Mode by the RESET_N Pin
62
Starting by the RESET_N Pin
62
Figure 3.7 Starting in the Single Boot Mode When Power Supply Is Stable
63
Starting in Single Boot Mode When Power Supply Is Stable
63
Power on Reset Circuit
64
Figure 3.8 Power on Reset Circuit
64
Operation at the Time of a Power Supply
64
Operation at the Time of Turn off
64
Turning off and Re-Turning on Power Supply
65
When Not Using External Reset Circuit and Internal LVD Reset Output
65
When Using External Reset Circuit or Internal LVD Reset Output
65
After Reset Release
65
Table 3.1 the Reset Factor and the Range Initialized
66
The Reset Factor and the Reset Range
66
4 Revision History
67
Table 4.1 Revision History
67
Restrictions on Product Use
68
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