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TMPR4937XBG-333
Toshiba TMPR4937XBG-333 Manuals
Manuals and User Guides for Toshiba TMPR4937XBG-333. We have
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Toshiba TMPR4937XBG-333 manual available for free PDF download: Manual
Toshiba TMPR4937XBG-333 Manual (552 pages)
64-Bit TX System RISC
Brand:
Toshiba
| Category:
Computer Hardware
| Size: 3.98 MB
Table of Contents
Table of Contents
5
Tmpr4937
43
Overview and Features
47
Overview
47
Features
47
Features of the TX49/H3 Core
48
Features of TX4937 Peripheral Functions
48
Configuration
53
TX4937 Block Diagram
53
Signals
55
Pin Signal Description
55
Signals Common to SDRAM and External Bus Interfaces
55
SDRAM Interface Signals
56
External Interface Signals
57
DMA Interface Signals
58
PCI Interface Signals
58
Serial I/O Interface Signals
60
Timer Interface Signals
60
Parallel I/O Interface Signals
60
AC-Link Interface Signals
61
Interrupt Signals
61
Extended EJTAG Interface Signals
62
Clock Signals
62
Initialization Signal
63
Test Signals
63
Power Supply Pins
63
Boot Configuration
64
Pin Multiplex
68
Address Mapping
69
TX4937 Physical Address Map
69
Register Map
70
Addressing
70
Ways to Access to Internal Registers
70
Configuration Registers
81
Detailed Description
81
Detecting G-Bus Timeout
81
Registers
82
Chip Configuration Register (CCFG) 0Xe000
83
Chip Revision ID Register (REVID) 0Xe008
86
Pin Configuration Register (PCFG) 0Xe010
87
Timeout Error Access Address Register (TOEA) 0Xe018
90
Clock Control Register (CLKCTR) 0Xe020
91
G-Bus Arbiter Control Register (GARBC) 0Xe030
93
Clocks
95
TX4937 Clock Signals
95
Power-Down Mode
99
Halt Mode and Doze Mode
99
Power Reduction for Peripheral Modules
99
Power-On Sequence
100
External Bus Controller
101
Features
101
Block Diagram
102
Detailed Explanation
103
External Bus Control Register
103
Global/Boot-Up Options
104
Address Mapping
105
External Address Output
106
Data Bus Size
107
Access Mode
109
Access Timing
113
Clock Options
119
Register
120
0X9010 (Ch. 2), 0X9018 (Ch. 3) 0X9020 (Ch. 4), 0X9028 (Ch. 5) 0X9030 (Ch. 6), 0X9038 (Ch. 7)
121
Timing Diagrams
124
ACE* Signal
125
Normal Mode Access (Single, 32-Bit Bus)
127
Normal Mode Access (Burst, 32-Bit Bus)
131
Normal Mode Access (Single, 16-Bit Bus)
133
Normal Mode Access (Burst, 16-Bit Bus)
137
Normal Mode Access (Single, 8-Bit Bus)
139
Normal Mode Access (Burst, 8-Bit Bus)
142
Page Mode Access (Burst, 32-Bit Bus)
144
External ACK Mode Access (32-Bit Bus)
146
READY Mode Access (32-Bit Bus)
152
Flash ROM, SRAM Usage Example
154
DMA Controller
157
Features
157
Block Diagram
158
Detailed Explanation
160
Transfer Mode
160
On-Chip Registers
161
External I/O DMA Transfer Mode
161
Internal I/O DMA Transfer Mode
164
Memory-Memory Copy Mode
165
Memory Fill Transfer Mode
165
Single Address Transfer
165
Dual Address Transfer
168
DMA Transfer
173
Chain DMA Transfer
174
Dynamic Chain Operation
176
Interrupts
177
Transfer Stall Detection Function
177
Arbitration Among DMA Channels
178
Restrictions in Access to PCI Bus
178
DMA Controller Registers
179
DMA Master Control Register (DM0MCR, DM1MCR)
181
DMA Channel Control Register (Dm0Ccrn, Dm1Ccrn)
183
DMA Channel Status Register (Dm0Csrn, Dm1Csrn))
187
DMA Source Address Register (Dm0Sarn, Dm1Sarn)
189
DMA Destination Address Register (Dm0Darn, Dm1Darn)
190
DMA Chain Address Register (Dm0Charn, Dm1Charn)
191
DMA Source Address Increment Register (Dm0Sairn, Dm1Sairn)
192
DMA Destination Address Increment Register (Dm0Dairn, Dm1Dairn)
193
DMA Count Register (Dm0Cntrn, Dm1Cntrn)
194
DMA Memory Fiill Data Register (DM0MFDR, DM1MFDR)
195
Timing Diagrams
196
Single Address Single Transfer from Memory to I/O (32-Bit ROM)
196
Single Address Single Transfer from Memory to I/O (16-Bit ROM)
197
Single Address Single Transfer from I/O to Memory (32-Bit SRAM)
198
Single Address Burst Transfer from Memory to I/O (32-Bit ROM)
199
Single Address Burst Transfer from I/O to Memory (32-Bit SRAM)
200
Single Address Single Transfer from Memory to I/O (16-Bit ROM)
202
Single Address Single Transfer from I/O to Memory (16-Bit SRAM)
203
Single Address Single Transfer from Memory to I/O (32-Bit Half Speed ROM)
204
Single Address Single Transfer from I/O to Memory (32-Bit Half Speed SRAM)
205
Single Address Single Transfer from Memory to I/O (64-Bit SRAM)
206
Single Address Single Transfer from I/O to Memory (64-Bit SDRAM)
207
Single Address Single Transfer from Memory to I/O of Last Cycle When DMADONE* Signal Is Set to Output
208
Single Address Single Transfer from Memory to I/O (32-Bit SDRAM)
209
Single Address Single Transfer from I/O to Memory (32-Bit SDRAM)
210
External I/O Device - SRAM Dual Address Transfer
211
External I/O Device - SDRAM Dual Address Transfer
213
External I/O Device (Non-Burst) - SDRAM Dual Address Transfer
215
SDRAM Controller
217
Characteristics
217
Block Diagram
218
Detailed Explanation
219
Supported SDRAM Configurations
219
Address Mapping
220
Initialization of SDRAM
225
Initialization of Memory Data, Ecc/Parity
226
Low Power Consumption Function
227
Bus Errors
228
Memory Read and Memory Write
228
Slow Write Burst
228
Clock Feedback
228
Ecc
229
Registers
233
0X8018 (Ch. 3)
234
SDRAM Timing Register (SDCTR) 0X8040
236
SDRAM Command Register (SDCCMD) 0X8058
238
ECC Control Register (ECCCR) 0Xa000
239
ECC Status Register (ECCSR) 0Xa008
241
Timing Diagrams
242
Single Read (64-Bit Bus)
242
Single Write (64-Bit Bus)
244
Burst Read (64-Bit Bus)
246
Burst Write (64-Bit Bus)
247
Burst Write (64-Bit Bus, Slow Write Burst)
248
Single Read (32-Bit Bus)
249
Single Write (32-Bit Bus)
251
Low Power Consumption and Power down Mode
253
SDRAM Usage Example
258
PCI Controller
259
Features
259
Overall
259
Initiator Function
259
Target Function
260
PCI Arbiter
260
PDMAC (PCI DMA Controller)
260
Block Diagram
261
Detailed Explanation
262
Terminology Explanation
262
On-Chip Register
262
Supported PCI Bus Commands
264
Initiator Access (G-Bus → PCI Bus Address Conversion)
266
Target Access (PCI Bus → G-Bus Address Conversion)
268
Post Write Function
270
Endian Switching Function
270
66 Mhz Operation Mode
271
Power Management
272
PDMAC (PCI DMA Controller)
273
Error Detection, Interrupt Reporting
276
PCI Bus Arbiter
278
PCI Boot
280
Set Configuration Space
281
PCI Clock
281
PCI Controller Control Register
282
ID Register (PCIID) 0Xd000
284
PCI Status, Command Register (PCISTATUS) 0Xd004
285
Class Code, Revision ID Register (PCICCREV) 0Xd008
288
PCI Configuration 1 Register (PCICFG1) 0Xd00C
289
P2G Memory Space 0 PCI Lower Base Address Register (P2GM0PLBASE) 0Xd010
290
P2G Memory Space 0 PCI Upper Base Address Register (P2GM0PUBASE) 0Xd014
291
P2G Memory Space 1 PCI Lower Base Address Register (P2GM1PLBASE) 0Xd018
291
P2G Memory Space 1 PCI Upper Base Address Register (P2GM1PUBASE) 0Xd01C
292
P2G Memory Space 2 PCI Base Address Register (P2GM2PBASE) 0Xd020
292
P2G I/O Space PCI Base Address Register (P2GIOPBASE) 0Xd024
293
Subsystem ID Register (PCISID) 0Xd02C
294
Capabilities Pointer Register (PCICAPPTR) 0Xd034
295
PCI Configuration 2 Register (PCICFG2) 0Xd03C
296
G2P Timeout Count Register (G2PTOCNT) 0Xd040
297
G2P Status Register (G2PSTATUS) 0Xd080
298
G2P Interrupt Mask Register (G2PMASK) 0Xd084
299
Satellite Mode PCI Status Register (PCISSTATUS) 0Xd088
300
PCI Status Interrupt Mask Register (PCIMASK) 0Xd08C
301
P2G Configuration Register (P2GCFG) 0Xd090
302
P2G Status Register (P2GSTATUS) 0Xd094
304
P2G Interrupt Mask Register (P2GMASK) 0Xd098
305
P2G Current Command Register (P2GCCMD) 0Xd09C
306
PCI Bus Arbiter Request Port Register (PBAREQPORT) 0Xd100
307
PCI Bus Arbiter Configuration Register (PBACFG) 0Xd104
309
PCI Bus Arbiter Interrupt Mask Register (PBAMASK) 0Xd10C
311
PCI Bus Arbiter Broken Master Register (PBABM) 0Xd110
312
PCI Bus Arbiter Current Grant Register (PBACGNT) 0Xd118
314
PCI Bus Arbiter Current State Register (PBACSTATE) 0Xd11C
315
G2P Memory Space 0 G-Bus Base Address Register (G2PM0GBASE) 0Xd120
317
G2P Memory Space 1 G-Bus Base Address Register (G2PM1GBASE) 0Xd128
318
G2P Memory Space 2 G-Bus Base Address Register (G2PM2GBASE) 0Xd130
319
G2P I/O Space G-Bus Base Address Register (G2PIOGBASE) 0Xd138
320
G2P Memory Space 0 Address Mask Register (G2PM0MASK) 0Xd140
321
G2P Memory Space 1 Address Mask Register (G2PM1MASK) 0Xd144
322
G2P Memory Space 2 Address Mask Register (G2PM2MASK) 0Xd148
323
G2P I/O Space Address Mask Register (G2PIOMASK) 0Xd14C
324
G2P Memory Space 0 PCI Base Address Register (G2PM0PBASE) 0Xd150
325
G2P Memory Space 1 PCI Base Address Register (G2PM1PBASE) 0Xd158
326
G2P Memory Space 2 PCI Base Address Register (G2PM2PBASE) 0Xd160
327
G2P I/O Space PCI Base Address Register (G2PIOPBASE) 0Xd168
328
PCI Controller Configuration Register (PCICCFG) 0Xd170
329
PCI Controller Status Register (PCICSTATUS) 0Xd174
332
PCI Controller Interrupt Mask Register (PCICMASK) 0Xd178
334
P2G Memory Space 0 G-Bus Base Address Register (P2GM0GBASE) 0Xd180
335
P2G Memory Space 1 G-Bus Base Address Register (P2GM1GBASE) 0Xd188
336
P2G Memory Space 2 G-Bus Base Address Register (P2GM2GBASE) 0Xd190
337
P2G I/O Space G-Bus Base Address Register (P2GIOGBASE) 0Xd198
338
G2P Configuration Address Register(G2PCFGADRS) 0Xd1A0
339
G2P Configuration Data Register (G2PCFGDATA) 0Xd1A4
340
G2P Interrupt Acknowledge Data Register (G2PINTACK) 0Xd1C8
341
G2P Special Cycle Data Register (G2PSPC) 0Xd1Cc
342
Configuration Data 0 Register (PCICDATA0) 0Xd1D0
343
Configuration Data 1 Register (PCICDATA1) 0Xd1D4
344
Configuration Data 2 Register (PCICDATA2) 0Xd1D8
345
Configuration Data 3 Register (PCICDATA3) 0Xd1Dc
346
PDMAC Chain Address Register (PDMCA) 0Xd200
347
PDMAC G-Bus Address Register (PDMGA) 0Xd208
348
PDMAC PCI Bus Address Register (PDMPA) 0Xd210
349
PDMAC Count Register (PDMCTR) 0Xd218
350
PDMAC Configuration Register (PDMCFG) 0Xd220
351
PDMAC Status Register (PDMSTATUS) 0Xd228
353
PCI Configuration Space Register
356
Capability ID Register (Cap_Id) 0Xdc
357
Next Item Pointer Register (Next_Item_Ptr) 0Xdd
358
Power Management Capability Register (PMC) 0Xde
359
Power Management Control/Status Register (PMCSR) 0Xe0
360
Serial I/O Port
361
Features
361
Block Diagram
362
Detailed Explanation
363
Overview
363
Data Format
363
Serial Clock Generator
365
Data Reception
367
Data Transmission
367
Flow Control
368
Reception Data Status
368
Reception Time out
369
Software Reset
369
Error Detection/Interrupt Signaling
370
Multi-Controller System
371
Registers
372
Line Control Register 0 (SILCR0) 0Xf300 (Ch. 0) Line Control Register 1 (SILCR1) 0Xf400 (Ch. 1)
373
Dma/Interrupt Control Register 0 (SIDICR0) 0Xf304 (Ch. 0) Dma/Interrupt Control Register 1 (SIDICR1) 0Xf404 (Ch. 1)
375
Dma/Interrupt Status Register 0 (SIDISR0) 0Xf308 (Ch. 0) Dma/Interrupt Status Register 1 (SIDISR1) 0Xf408 (Ch. 1)
377
Status Change Interrupt Status Register 0 (SISCISR0) 0Xf30C (Ch. 0) Status Change Interrupt Status Register 1 (SISCISR1) 0Xf40C (Ch. 1)
379
FIFO Control Register 0 (SIFCR0) 0Xf310 (Ch. 0) FIFO Control Register 1 (SIFCR1) 0Xf410 (Ch. 1)
380
Flow Control Register 0 (SIFLCR0) 0Xf314 (Ch. 0) Flow Control Register 1 (SIFLCR1) 0Xf414 (Ch. 1)
381
Baud Rate Control Register 0 (SIBGR0) 0Xf318 (Ch. 0) Baud Rate Control Register 1 (SIBGR1) 0Xf418 (Ch. 1)
382
Transmit FIFO Register 0 (SITFIFO0) 0Xf31C (Ch. 0) Transmit FIFO Register 1 (SITFIFO1) 0Xf41C (Ch. 1)
383
Receive FIFO Register 0 (SIRFIFO0) 0Xf320 (Ch. 0) Receive FIFO Register 1 (SIRFIFO1) 0Xf420 (Ch. 1)
384
Timer/Counter
385
Features
385
Block Diagram
386
Detailed Explanation
387
Overview
387
Counter Clock
387
Counter
388
Interval Timer Mode
388
Pulse Generator Mode
390
Watchdog Timer Mode
391
Registers
393
Timer Interrupt Status Register N (Tmtisrn) TMTISR0 0Xf004 TMTISR1 0Xf104 TMTISR2 0Xf204
395
TMCPRA2 0Xf208
396
Compare Register Bn (Tmcprbn) TMCPRB0 0Xf00C TMCPRB1 0Xf10C
397
TMITMR2 0Xf210
398
Pulse Generator Mode Register N (Tmpgmrn) TMPGMR0 0Xf000 TMPGMR1 0Xf130
400
Watchdog Timer Mode Register N (Tmwtmrn) TMWTMR2 0Xf240
401
TMTRR2 0Xf2F0
402
Parallel I/O Port
403
Characteristics
403
Block Diagram
403
Detailed Description
404
Selecting PIO Pins
404
General-Purpose Parallel Port
404
Registers
404
PIO Output Data Register (PIODO) 0Xf500
405
PIO Input Data Register (PIODI) 0Xf504
405
PIO Direction Control Register (PIODIR) 0Xf508
406
PIO Open Drain Control Register (XPIOOD) 0Xf50C
406
AC-Link Controller
407
Features
407
Configuration
408
Functional Description
409
CODEC Connection
409
Boot Configuration
410
Usage Flow
411
AC-Link Start up
413
CODEC Register Access
414
Sample-Data Transmission and Reception
415
GPIO Operation
420
Interrupt
421
AC-Link Low-Power Mode
421
Registers
422
ACLC Control Enable Register 0Xf700
423
ACLC Control Disable Register 0Xf704
426
ACLC CODEC Register Access Register 0Xf708
428
ACLC Interrupt Status Register 0Xf710
429
ACLC Interrupt Masked Status Register 0Xf714
431
ACLC Interrupt Enable Register 0Xf718
431
ACLC Interrupt Disable Register 0Xf71C
431
ACLC Semaphore Register 0Xf720
432
ACLC GPI Data Register 0Xf740
433
ACLC GPO Data Register 0Xf744
434
ACLC Slot Enable Register 0Xf748
435
ACLC Slot Disable Register 0Xf74C
437
ACLC FIFO Status Register 0Xf750
438
ACLC DMA Channel Selection Register 0Xf784
441
ACLC Audio PCM Output Data Register 0Xf7A0
442
ACLC Center Data Register 0Xf7A8
443
ACLC Audio PCM Input Data Register 0Xf7B0
444
ACLC Modem Input Data Register 0Xf7Bc
445
ACLC Revision ID Register 0Xf7Fc
446
Interrupt Controller
447
Characteristics
447
Block Diagram
448
Detailed Explanation
450
Interrupt Sources
450
Interrupt Request Detection
451
Interrupt Level Assigning
451
Interrupt Priority Assigning
452
Interrupt Notification
453
Clearing Interrupt Requests
453
Interrupt Requests
454
Registers
456
Interrupt Detection Enable Register (IRDEN) 0Xf600
457
Interrupt Detection Mode Register 0 (IRDM0) 0Xf604
458
Interrupt Detection Mode Register 1 (IRDM1) 0Xf608
460
Interrupt Level Register 0 (IRLVL0) 0Xf610
463
Interrupt Level Register (IRLVL1) 0Xf614
465
Interrupt Level Register 2 (IRLVL2) 0Xf618
467
Interrupt Level Register 3 (IRLVL3) 0Xf61C
468
Interrupt Level Register 4 (IRLVL4) 0Xf620
470
Interrupt Level Register 5 (IRLVL5) 0Xf624
472
Interrupt Level Register 6 (IRLVL6) 0Xf628
474
Interrupt Level Register 7 (IRLVL7) 0Xf62C
476
Interrupt Mask Level Register (IRMSK) 0Xf640
478
Interrupt Edge Detection Clear Register (IREDC) 0Xf660
479
Interrupt Pending Register (IRPND) 0Xf680
480
Interrupt Current Status Register (IRCS) 0Xf6A0
483
Interrupt Request Flag Register 0 (IRFLAG0) 0Xf510
486
Interrupt Request Flag Register 1 (IRFLAG1) 0Xf514
486
Interrupt Request Polarity Control Register (IRPOL) 0Xf518
487
Interrupt Request Control Register (IRRCNT) 0Xf51C
488
Interrupt Request Internal Interrupt Mask Register (IRMASKINT) 0Xf520
489
Interrupt Request External Interrupt Mask Register (IRMASKEXT) 0Xf524
490
Removed
491
Removed
495
Removed
497
Extended EJTAG Interface
499
JTAG Boundary Scan Test
500
JTAG Controller and Register
500
Instruction Register
501
Boundary Scan Register
501
Device ID Register
504
Initializing the Extended EJTAG Interface
505
Absolute Maximum Rating (*1)
507
Recommended Operating Conditions
507
DC Characteristics of Pins Other than PCI Interface Pins
508
DC Characteristics of PCI Interface Pins
509
PLL Power
510
PLL Power Connection Example
510
AC Characteristics
511
MASTERCLK AC Characteristics
511
Power on AC Characteristics
511
SDRAM Interface AC Characteristics
512
External Bus Interface AC Characteristics
514
PCI Interface AC Characteristics (66 Mhz)
515
PCI Interface AC Characteristics (33 Mhz)
515
PCI EEPROM Interface AC Characteristics
517
DMA Interface AC Characteristics
517
Interrupt Interface AC Characteristics
518
SIO Interface AC Characteristics
519
Timer Interface AC Characteristics
519
PIO Interface AC Characteristics
520
AC-Link Interface AC Characteristics
520
Pinout and Package Information
521
Pinout Diagram
521
Package Dimensions
529
Notes on Use of TMPR4937
531
Notes on TX49/H3 Core
531
Notes on External Bus Controller
533
Notes on DMA Controller
533
Note on PCI Controller
536
Notes on Serial I/O Port
540
Parts Number When Ordering
541
Appendix Atx49/H3 Core Supplement
543
Processor ID
543
Interrupts
543
Bus Snoop
543
Halt/Doze Mode
543
Memory Access Order
543
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