Table of Contents
Advertisement
9.4.2
SDRAM Timing Register (SDCTR)
63
47
31
29
28
BC
ACP
R/W
R/W
1
0
1
1
15
14
13
12
DA
SWB
Reserved
R/W
R/W
1
1
Bit
Mnemonic
Field Name
63:34
—
33:32
DIA
Write Active
Period
31:29
BC
Bank Cycle Time
28:27
ACP
Active Command
Time
26
PT
Precharge Time
25
RCD
RAS-CAS Delay
1
t
= Clock cycle
CK
2
t
is used during (i) refresh cycle time, (ii) single Read, (iii) two transfer burst Reads. The bank cycle time is t
RC
t
+ 1t
if t
+ t
< t
RP
CK
RAS
RP
RC
Reserved
Reserved
27
26
25
24
PT
RCD
ACE
PDAE
R/W
R/W
R/W
R/W
1
1
1
0
11
—
Reserved
Data In to Active(t
DAL
Specifies the period from the last Write data to the Active command.
00: Reserved
1
01: 4 t
CK
10: 5 t
CK
11: 6 t
CK
Bank Cycle Time (t
RC
Specifies the bank cycle time.
000: 5 t
100: 9 t
CK
CK
001: 6 t
101: 10 t
CK
010: 7 t
110: Reserved
CK
011: 8 t
111: Reserved
CK
Active Command Period (t
Specifies the active command time.
00: 3 t
CK
01: 4 t
CK
10: 5 t
CK
11: 6 t
CK
Precharge Time (t
RP
Specifies the precharge time.
0: 2 t
CK
1: 3 t
CK
RAS to CAS Delay (t
Specifies the RAS - CAS delay.
0: 2 t
CK
1: 3 t
CK
Figure 9.4.2 SDRAM Timing Register (1/2)
in the case of (ii) (iii).
Chapter 9 SDRAM Controller
0x8040
23
22
RC
R/W
0
0
0
0
RP
R/W
0x30C
Description
) (Default: 11)
) (Default: 101)
2
CK
) (Default: 11)
RAS
) (Default: 1)
) (Default: 1)
RCD
9-20
48
:Type
:Initial value
34
33
32
DIA
R/W
:Type
1
1
:Initial value
18
17
16
CASL
DRB
R/W
R/W :Type
0
0
1
0
:Initial value
0
:Type
:Initial value
Read/Write
⎯
R/W
R/W
R/W
R/W
R/W
RAS
+
Advertisement
Table of Contents
