Toshiba TX3904 RISC Processor Reference Manuals

Manuals and User Guides for Toshiba TX3904 RISC Processor Reference. We have 1 Toshiba TX3904 RISC Processor Reference manual available for free PDF download: User Manual

Toshiba TX3904 User Manual

Toshiba TX3904 User Manual (230 pages)

32bit RISC Microprocessor

Brand: Toshiba | Category: Computer Hardware | Size: 1.49 MB

Table of Contents

Table of Contents
3
1 Introduction

9
2 Features

15
3 Configuration

17
4 Pins

19
- Positions of Pins
  19
- Functions of Pins
  21
5 Address Maps

25
- Register Map
  26
- Chip Configuration Register
  29
  - PIO2 and PIO1
    30
  - Error Processing
    31
  - Connection of External Bus Master
    32
  - INT[7:0] Active Status Set-Up
    33
6 Clock

35
- Doze Mode
  36
- Status Shifting
  37
- Operations of each Block in the each Modes
  38
7 Bus Operations

39
- Single Read Operation
  43
- Burst Read Operation
  45
- Single Write Operation
  47
- Bus Error
  49
- Bit Bus Mode
  51
- Half Speed Bus Mode
  53
- Bus Arbitration
  54
  - Release of Bus Ownership
    55
  - Kinds of Bus Ownership
    56
  - Snoop Function
    57
- Interrupts
  58
8 Dram Controller (Dramc)

59
- Features
  59
- Block Diagrams
  60
- Registers
  61
- Explanations of Registers
  62
- Operations
  73
  - Address Multiplex
    74
  - Operation Modes
    75
  - Bit Static Bus Sizing
    76
  - Page Mode Support and Page Hit Detection
    77
  - Arbiter
    78
- Timing Diagrams
  79
- External Circuit Connections
  91
9 Rom Controller (Romc)

93
10 Dma Controller (Dmac)

124
- Configuration
  125
- DMAC Internal Blocks
  126
- Registers
  128
  - DMA Control Register (DCR)
    129
  - Channel Control Register (Ccrn)
    130
  - Channel Status Register (Csrn)
    134
  - Source Address Register (Sarn)
    137
  - Destination Address Register (Darn)
    138
  - Byte Count Register (Bcr0N)
    139
  - Next Byte Count Register (NCR0/1)
    140
  - Data Holding Register (DHR)
    141
- Functions
  142
  - Transfer Requests
    146
  - Address Modes
    150
  - Burst Transfer
    155
  - Channel Operation
    156
  - Endian Switch Function
    160
- Operations
  161
  - Single Address Mode
    164
  - Input of DONE* Signal
    167
  - Output of DONE* Signal
    168
11 Interrupts

170
- Configuration
  171
- Functions
  172
  - Interrupt Detection
    173
- Registers
  174
12 Serial Ports (Sio)

178
- Registers
  180
  - Line Control Register (Slcrn)
    181
  - Line Status Register (Slsrn)
    183
  - Dma/Interrupt Control Register (Sdicrn)
    184
  - Dma/Interrupt Status Register (Sdisrn)
    186
  - FIFO Control Register (Sfcrn)
    188
  - Baudrate Control Register (Sbgrn)
    189
  - Transmit FIFO Buffer (Tfifon)
    190
- Operations
  191
  - Serial Clock Generator
    193
  - Receiver Controller
    195
  - Hand Shake Function
    196
  - Parity Control
    197
- Timing Explanations
  199
  - Operation at the Time of Receiving (8 and 9 Bit Length Multi-Controller System
    200
  - Transmit Halt Timing by CTS
    202
13 Timers/Counters

204
- Registers
  206
  - Watchdog Timer Mode Register 2 (WTMR2)
    213
- Operations
  218
  - Pulse Generator Mode
    221
  - Watchdog Timer Mode
    223
- Timing Explanations
  224
  - Pulse Generator Mode F/F Output Timing
    225
14 Io Ports (Pio)

226
- Registers
  227

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