Table of Contents
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TXZ+ Family
TMPM4K Group(2)
Clock Control and Operation Mode
List of Figures
Figure 1.1 Clock system diagram............................................................................................................. 12
Figure 1.2 Mode State Transition ............................................................................................................. 25
Figure 1.3 NORMAL >>> STOP1 >>> NORMAL Operation mode transition ......................................... 29
Figure 2.1 TMPM4KxF10A ....................................................................................................................... 44
Figure 2.2 TMPM4KxFDA ........................................................................................................................ 45
Figure 2.3 TMPM4KxFYA ........................................................................................................................ 46
Figure 2.4 TMPM4KxFWA ....................................................................................................................... 47
Figure 2.5 Single Chip Mode .................................................................................................................... 49
Figure 2.6 Single Boot Mode .................................................................................................................... 50
Figure 3.1 The reset operation by a Power On Reset Circuit .................................................................. 57
Figure 3.2 Reset operation by a RESET_N pin (1) .................................................................................. 58
Figure 3.3 Reset operation by a RESET_N pin (2) .................................................................................. 59
Figure 3.4 Reset operation by LVD reset ................................................................................................. 60
Figure 3.5 Warm reset operation ............................................................................................................. 61
Figure 3.6 When the power supply is on, starting in Single Boot Mode by the RESET_N pin ............... 62
Figure 3.7 Starting in the Single Boot Mode when power supply is stable ............................................. 63
Figure 3.8 Power On Reset Circuit .......................................................................................................... 64
List of Tables
Table 1.1 Details of [CGPLL0SEL]<PLL0SET[23:0]> setup .................................................................... 15
Table 1.2 PLL correction (example) ......................................................................................................... 15
Table 1.3 PLL0SET setting value (example) ........................................................................................... 16
Table 1.4 Clock domains of CPU and peripherals ................................................................................... 18
Table 1.5 Time interval for changing System clock ................................................................................. 18
Table 1.6 Example of operating frequency .............................................................................................. 18
Table 1.7 Operating frequency examples of High speed and Middle speed system clocks ................... 19
Table 1.8 Time interval for changing prescaler clocks ............................................................................ 21
Table 1.9 Low Power Consumption mode selection................................................................................ 23
Table 1.10 Block operation status in each Low Power Consumption mode ........................................... 24
Table 1.11 Release source list ................................................................................................................. 27
Table 1.12 Warming-up ............................................................................................................................ 28
Table 1.13 [CGFSYSMENA] register corresponding to each product ..................................................... 40
Table 1.14 [CGFSYSMENB] register corresponding to each product ..................................................... 41
Table 1.15 [CGFSYSENA] register corresponding to each product ........................................................ 42
Table 1.16 [CGFCEN] register corresponding to each product ............................................................... 42
Table 2.1 Single Chip Mode ..................................................................................................................... 51
Table 2.2 Single Boot Mode ..................................................................................................................... 51
Table 2.3 Single Chip Mode ..................................................................................................................... 52
Table 2.4 Single Boot Mode ..................................................................................................................... 52
Table 2.5 Single Chip Mode ..................................................................................................................... 53
Table 2.6 Single Boot Mode ..................................................................................................................... 53
Table 2.7 Single Chip Mode ..................................................................................................................... 54
Table 2.8 Single Boot Mode ..................................................................................................................... 54
Table 2.9 Connection of peripheral function ............................................................................................ 55
Table 3.1 The reset factor and the range initialized................................................................................. 66
Table 4.1 Revision History ....................................................................................................................... 67
5 / 68
2023-12-25
Rev. 3.0
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