Table of Contents
Advertisement
19.3 Operations
19.3.1
Operation
The RTC contains five 8-bit ripple counters connected in series. The first counter counts on each
C32K clock, while each successive counter only counts when the previous count stage has reached a
count of "0xFF". Once the counters reach a count of "0xFFFFFFFFFFF", the RTCINT interrupt will
assert to indicate that the counter is "rolling over". Given a 44-bit counter for the RTC and an input
clock C32K of 32.768 kHz, the time until RTCINT interrupt will assert is 6213 days.
The software can generate an alarm interrupt(ALARMINT) by setting the ALARM[43:0] bits in the
Alarm Register.
ALARMINT will be triggered. The value of the RTC counter can be read via the RTC Register.
19.3.2
Interrupt
The RTC has two types interrupt sources. OR signal of them connects to the internal Interrupt
Controller (IRC). Please check RTC Interrupt Status Register (RTCINT) to know which type of
interrupt occurred.
Type
RTCINT
ALARMINT
RTCINT:
This interrupt is set 44 bits of the RTC counter reach a value of "0xFFFFFFFFFFF" to alert the
software that the counter is "rolling over".
ALARMINT:
This interrupt is set whenever the RTC counter reaches a count that is equal to the value of the
ALARM[43:0] bits set in the ALAMHI and ALARMLO Registers.
19.4 Registers
All registers should be accessed only as full word (32-bit) accesses. Any other type of access produces an
undefined result. Please write "0" to the undefined bit.
Reference
Address
19.4.1
0xF900
19.4.2
0xF904
19.4.3
0xF908
19.4.4
0xF90C
19.4.5
0xF910
19.4.6
0xF914
Whenever the RTC becomes equal to the value set in the Alarm Register, the
Status Bits
RTCINT in RTCINT
ALARMINT in RTCINT
Table 19.4.1 RTC Module Registers
Bit Width
Register Symbol
32-bit
RTCHI
32-bit
RTCLO
32-bit
ALARMHI
32-bit
ALARMLO
32-bit
RTCCTRL
32-bit
RTCINT
19-3
Chapter 19 Real Time Clock (RTC)
Mask-able Bit
DSRTCINT in RTCCTRL
DSALINT in RTCCTRL
RTC Register (High)
RTC Register (Low)
Alarm Register (High)
Alarm Register (Low)
RTC Control Register
RTC Interrupt Status Register
Register Name
Advertisement
Table of Contents
