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Toshiba 27WLT56B Service Manual
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Toshiba 27WLT56B Service Manual

Toshiba 27WLT56B Service Manual

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TOSHIBA
27WLT56B
SERVICE MANUAL

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Summary of Contents for Toshiba 27WLT56B

  • Page 1 TOSHIBA 27WLT56B SERVICE MANUAL...

  • Page 2: Table Of Contents

    TABLE OF CONTENTS INTRODUCTION ............................1 TUNER..............................1 IF PART (TDA9886) ..........................1 MULTI STANDARD SOUND PROCESSOR .................... 2 VIDEO SWITCH TEA6415 ........................2 AUDIO AMPLIFIER STAGE WITH TPA3002D2 ..................2 MAIN POWER SUPPLY (SMPS) AND POWER INTERFACE BOARD ..........3 MICROCONTROLLER ..........................
  • Page 3 SERVICE MENU SETTINGS ......................... 58 14.1. display menu ........................... 58 14.2. calibration menu ..........................60 14.3. deinterlacer menu..........................62 14.4. factory settings menu ........................64 BLOCK DIAGRAMS ..........................65 CIRCUIT DIAGRAMS ..........................67 27” TFT TV Service Manual 05/09/2005...

  • Page 4: Introduction

    1. INTRODUCTION 27” TFT IDTV is a progressive TV control system with built-in de-interlacer and scaler. It uses a 1280*720 panel with 16:9 aspect ratio.The TV is capable of operation in PAL, SECAM, NTSC (playback) colour standards and multiple transmission standards as B/G, D/K, I/I’, and L/L’ including German and NICAM stereo.

  • Page 5: Multi Standard Sound Processor

    VIF amplifier, Tuner and VIF-AGC, VIF-AGC detector, Frequency Phase-Locked Loop (FPLL) detector, VCO and divider, Digital acquisition help and AFC, Video demodulator and amplifier, Sound carrier trap, SIF amplifier, SIF-AGC detector, Single reference QSS mixer, AM demodulator, FM demodulator and acquisition I²C help, Audio amplifier and mute time constant, -bus transceivers and MAD (module address), Internal...

  • Page 6: Main Power Supply (Smps) And Power Interface Board

    7. MAIN POWER SUPPLY (SMPS) AND POWER INTERFACE BOARD The DC voltages required at various parts of the chassis and inverters are provided by an main power supply unit and power interface board. The main power supply unit is designed for 24V and 12V DC supply.

  • Page 7: Ic Descriptions And Internal Block Diagram

    K3953M: Standard: • B/G • D/K • I • L/L’ Features TV IF video filter with Nyquist slopes at 33,90 MHz and 38,90 MHz Constant group delay Suitable for CENELEC EN 55020 Terminals Tinned CuFe alloy Pin configuration 1 Input 2 Input - ground 3 Chip carrier - ground 4 Output...

  • Page 8: Tda9886

    TDA9886 12.1. 12.1.1. General Description The TDA9885 is an alignment-free single standard (without positive modulation) vision and sound IF signal PLL. 12.1.2. Features • 5 V supply voltage • Gain controlled wide-band Vision Intermediate Frequency (VIF) amplifier (AC-coupled) • Multistandard true synchronous demodulation with active carrier regeneration (very linear demodulation, good intermodulation figures, reduced harmonics, excellent pulse response) •...

  • Page 9: Tea6415C

    output 2 (open-collector) SIF1 SIF differential input 1 SIF2 SIF differential input 2 TEA6415C 12.2. 12.2.1. General Description The main function of the IC is to switch 8 video input sources on 6 outputs. Each output can be switched on only one of each input. On each input an alignment of the lowest level of the signal is made (bottom of synch.

  • Page 10: 24C32A

    24C32A 12.3. 12.3.1. Features • Voltage operating range: 4.5V to 5.5V - Maximum write current 3 mA at 5.5V - Standby current 1 mA typical at 5.0V • 2-wire serial interface bus, I compatible • 100 kHz and 400 kHz compatibility •...

  • Page 11: Saa5264

    12.3.4. Functional Descriptions The 24C32A supports a Bi-directional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus must be controlled by a master device which generates the Serial Clock (SCL), controls the bus access, and generates the START and STOP conditions, while the 24C32A works as slave.
  • Page 12 P3.2/ADC2 P3.3/ADC3 P3.4/PWM7 output for 6-bit PWM7 core ground Port 0: 8-bit programmable bidirectional port SCL(NVRAM) C-bus Serial Clock input to Non-Volatile RAM SDA(NVRAM) C-bus Serial Data input/output (Non-Volatile RAM) P0.2 input/output for general use P0.3 input/output for general use P0.4 input/output for general use P0.5...

  • Page 13: Lm317

    C-bus Serial Data input from (application) input/output for general use P1.4 input/output for general use P1.5 LM317 12.5. 12.5.1. General Description The LM117/LM217/LM317 are monolithic integrated circuit in TO-220, ISOWATT220, TO-3 and D PAK packages intended for use as positive adjustable voltage regulators. They are designed to supply more than 1.5A of load current with an output voltage adjustable over a 1.2 to 37V range.

  • Page 14: Tlc7733

    12.6.3. Pin connections DIP Pin connections CO Pin connections NC: Not connected Signal names Serial data Address Input/Output Serial Clock (I C mode) Supply voltage Ground VCLK Clock transmit only mode TLC7733 12.7. 12.7.1. Description The TLC77xx family of micropower supply voltage supervisors are designed for reset control, primarily in microcomputer and microprocessor systems.

  • Page 15: 74Lvc257A

    74LVC257A 12.8. 12.8.1. Features Wide supply voltage range of 1.2 to 3.6 V In accordance with JEDEC standard no. 8-1A CMOS lower power consumption Direct interface with TTL levels Output drive capability 50 _ transmission lines at 85°C 5 Volt tolerant inputs/outputs, for interfacing with 5 Volt logic 12.8.2.

  • Page 16: Lm1117

    12.9.4. Pin Description PIN NUMBER SYMBOL DESCRIPTION 1, 3, 5, 9, 11, 13 1A – 6A Data inputs 2, 4, 6, 8, 10, 12 1Y – 6Y Data outputs Ground (0V) Positive supply voltage LM1117 12.10. 12.10.1. General Description The LM1117 is a series of low dropout voltage regulators with a dropout of 1.2V at 800mA of load current.

  • Page 17: Irf7314- Irf7316

    IRF7314- IRF7316 12.11. Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications.

  • Page 18: Mc34063A

    Junction and Storage Temperature Range -55 to + 150 °C MC34063A 12.12. 1.5 A, Step-Up/Down/Inverting Switching Regulators The MC34063A Series is a monolithic control circuit containing the primary functions required for DC−to−DC converters. These devices consist of an internal temperature compensated reference, comparator, controlled duty cycle oscillator with an active current limit circuit, driver and high current output switch.

  • Page 19: Lm2576- 52Khz Simple 3A Buck Regulator

    LM2576- 52kHz Simple 3A Buck Regulator 12.13. 12.13.1. General Description The LM2576 series of monolithic integrated circuits provide all the active functions for a step-down (buck) switching regulator. Fixed versions are available with a 3.3V, 5V, or 12V fixed output. Adjustable versions have an output voltage range from 1.23V to 37V. Both versions are capable of driving a 3A load with excellent line and load regulation.

  • Page 20: Ds90C385

    • Wide output voltage range 1.23V to 37V • Requires only 4 external components • 52kHz fixed frequency internal oscillator • Low power standby mode I typically < 200⎧A • 80% efficiency (adjustable version typically > 80%) • Uses readily available standard inductors •...
  • Page 21 • Up to 2.38 Gbps throughput • Up to 297.5 Megabytes/sec bandwidth • 345 mV (typ) swing LVDS devices for low EMI • PLL requires no external components • Compatible with TIA/EIA-644 LVDS standard • Low profile 56-lead or 48-lead TSSOP package •...

  • Page 22: Msp34X1G

    MSP34X1G 12.15. MSP3411G Multistandard Sound Processor Family 12.15.1. Introduction The MSP 34x1G family of single-chip Multistandard Sound Processors covers the sound processing of all analog TV-Standards worldwide, as well as the NICAM digital sound standards. The full TV sound processing, starting with analog sound IF signal-in, down to processed analog AF-out, is performed on a single chip.
  • Page 23 12.15.2. Features • 3D-PANORAMA virtualizer (approved by Dolby Laboratories) with noise generator • PANORAMA virtualizer algorithm • Standard Selection with single I C transmission • Automatic Sound Selection (mono/stereo/bilingual), • Automatic Carrier Mute function • Interrupt output programmable (indicating status change) •...
  • Page 24 AVSUP Analog power supply 5V AVSUP Analog power supply 5V Not connected Not connected AVSS Analog ground AVSS Analog ground MONO_IN Mono input Not connected Reference voltage IF A/D VREFTOP converter SC1_IN_R SCART 1 input, right SC1_IN_L SCART 1 input, left ASG1 AHVSS Analog Shield Ground 1...

  • Page 25: Tpa3002D

    TPA3002D 12.16. 12.16.1. Description The TPA3002D2 is a 9-W (per channel) efficient, Class-D audio amplifier for driving bridged-tied stereo speakers. The TPA3002D2 can drive stereo speakers as low as 8 &. The high efficiency of the TPA3002D2 eliminates the need for external heatsinks when playing music. FEATURES - 9-W/Ch Into an 8-Ω...

  • Page 26: Pi5V330

    • High slew rate • Low distortion • Large output voltage swing. 12.17.3. Pinning SYMBOL DESCRIPTION OUTA Output A INA(neg) Inverting input A INA(pos) Non-inverting input A Negative supply INB(pos) Non-inverting input B INB(neg) Inverting input B OUTB Output B Positive supply PI5V330 12.18.
  • Page 27 12.19.3. Pin Descriptions 27” TFT TV Service Manual 05/09/2005...

  • Page 28: Saa7118E

    SAA7118E 12.20. 12.20.1. General Description The SAA7118E is a video capture device for applications at the image port of VGA controllers. Philips X-VIP is a new multistandard comb filter video decoder chip with additional component processing, providing high quality, optionally scaled, video. The SAA7118E is a combination of a four-channel analog preprocessing circuit including source selection, anti-aliasing filter and ADC, an automatic clamp and gain control, a Clock Generation Circuit (CGC), a digital multistandard decoder containing two-dimensional chrominance/luminance separation...
  • Page 29 • Fast blanking between CVBS and synchronous component inputs • Digital RGB to Y-C matrix. Video scaler • Horizontal and vertical downscaling and upscaling to randomly sized windows • Horizontal and vertical scaling range: variable zoom to 1/64 (icon) (note: H and V zoom are restricted by the transfer data rates) •...
  • Page 30 XPD0 LSB of expansion port data XPD2 MSB - 5 of expansion port data XPD4 MSB - 3 of expansion port data XPD6 MSB - 1 of expansion port data TEST1 I/pu do not connect, reserved for future extensions and for testing: scan input TEST2 I/pu...
  • Page 31 ground for analog inputs AI3x SSA3 HPD1 MSB - 6 of host port data I/O, extended C input for expansion port, extended C output for image port HPD3 MSB - 4 of host port data I/O, extended C input for expansion port, extended C output for image port HPD2...
  • Page 32 digital ground 11 (peripheral cells) SSD11 digital ground 12 (core) SSD12 RTCO O/st/pd real-time control output; contains information about actual system clock frequency, field rate, odd/even sequence, decoder status, subcarrier frequency and phase and PAL sequence; the RTCO pin is enabled via I C-bus bit RTCE;...

  • Page 33: Tps72501

    I/O/od serial data input/output (I 2 C-bus) AMCLK audio master clock output, up to 50% of crystal clock ALRCLK O/st/pd audio left/right clock output; can be strapped to supply via a 3.3 kW resistor to indicate that the default 24.576 MHz crystal (ALRCLK = 0; internal pull-down) has been replaced by a 32.110 MHz crystal (ALRCLK = 1);...
  • Page 34 ease of power dissipation, make it ideal for telecom boards, modem banks, and other noise sensitive applications. 12.21.2. Features • 1-A Output Current • Available in 1.5-V, 1.6-V, 1.8-V, 2.5-V Fixed-Output and Adjustable Versions (1.2-V to 5.5-V) • Input Voltage Down to 1.8 V •...

  • Page 35: Tsop1136

    TSOP1136 12.22. PCF8591 12.23. 12.23.1. General Description The PCF8591 is a single-chip, single-supply low power 8-bit CMOS data acquisition device with four analog inputs, one analog output and a serial I C-bus interface. Three address pins A0, A1 and A2 are used for programming the hardware address, allowing the use of up to eight devices connected to the I C-bus without additional hardware.

  • Page 36: Pw1231

    • On-chip track and hold circuit • 8-bit successive approximation A/D conversion • Multiplying DAC with one analog output. 12.23.3. Pinning SYMBOL DESCRIPTION AINO analog inputs (A/D converter) AIN1 AIN2 AIN3 hardware address negative supply voltage C-bus data input/output C-bus clock input oscillator input/output external/internal switch for oscillator input AGND...

  • Page 37: Pw181

    • Rear Projection TVs • Plasma Displays • LCD Multimedia Monitors • Multimedia Projectors PW181 12.25. 12.25.1. General Description The PW181 ImageProcessor is a highly integrated “system-on-a-chip” that interfaces computer graphics and video inputs in virtually any format to a fixed-frequency flat panel display. Computer and video images from NTSC/PAL to WUXGA at virtually any refresh rate can be resized to fit on a fixed-frequency target display device with any resolution up to WUXGA.

  • Page 38: Sil1169

    • Digital Television SIL1169 12.26. 12.26.1. General Description The SiI 1169 receiver uses PanelLink Digital technology to support high-resolution digital displays for PC and HDTV applications. The SiI 1169 device features High-bandwidth Digital Content Protection HDCP) for secure delivery of high-definition video, and comes with integrated, pre-programmed HDCP eys to simplify manufacturing and provide the highest level of security.

  • Page 39: Sdram 4M X 16 (Mt48Lc4M16A2Tg-75)

    SDRAM 4M x 16 (MT48LC4M16A2TG-75) 12.27. 12.27.1. General Description The Micron ® 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 67,108,864 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 16,777,216-bit banks is orga-nized as 4,096 rows by 1,024 columns by 4 bits.
  • Page 40 12.27.2. Features • PC66-, PC100-, and PC133-compliant • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal banks for hiding row access/precharge • Programmable burst lengths: 1, 2, 4, 8, or full page •...

  • Page 41: Flash 16Mbit

    – Address input (A12) for the 256Mb and 512Mb devices 3, 9, 43, 49 Supply DQ Power: Isolated DQ power on the die for improved noise immunity. 6, 12, 46, 52 Supply DQ Ground: Isolated DQ ground on the die for improved noise immunity.

  • Page 42: Asm3P2814

    ASM3P2814 12.29. 12.29.1. Description The ASM3P28XX devices are versatile spread spectrum frequency modulators designed specifically for a wide range of input clock frequencies from 10MHz to 40MHz. The ASM3P28XX reduces electromagnetic interference (EMI) at the clock source, allowing system wide reduction of EMI of down stream clock and data dependent signals.

  • Page 43: 74Lx1G86

    74LX1G86 12.30. 12.30.1. Features • 5V TOLERANT INPUTS • HIGH SPEED: t = 5ns (MAX.) at VCC = 3V • LOW POWER DISSIPATION: ICC = 1A (MAX.) at TA = 25°C • POWER DOWN PROTECTION ON INPUTS AND OUTPUTS • SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) at VCC = 3V •...

  • Page 44: 74Hct4053

    74HCT4053 12.31. 12.31.1. General Description 74HCT4053 is a high-speed Si-gate CMOS device, which has a triple 2-channel analogue multiplexer / demultiplexer with a common enable input. and GND are the supply voltage pins for the digital control inputs The V to GND ranges are 4.5 to 5.5 V for HCT.

  • Page 45: Ic Descriptions (For Digital)

    13. IC DESCRIPTIONS (FOR DIGITAL) STI5518 24C32 MAX232_SMD STV0360 74HCU04 MAX809 TSH22 TDCC2345TV39A CS4334 STV0700 AMIC A43L2616 MX29LV160T STI5518 13.1. 13.1.1. General Description The STi5518 is a highly integrated single-chip decoder, designed for use in feature-rich mass-market set-top boxes. It integrates a high-performance 32-bit CPU, a dedicated block for DVB/DirecTV transport demultiplexing and descrambling, modules for MPEG-2 video and audio decoding with 3D- surround and MP3 support, advanced display and graphics features, a digital video encoder and all of the system peripherals required in a typical low-cost interactive receiver.

  • Page 46: 74Hcu04

    74HCU04 13.3. 13.3.1. General Description The M54/74HCU04 is a high speed CMOS HEX INVERTER (SINGLE STAGE) fabricated in silicon gate MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. As the internal circuit is composed of a single stage inverter, it can be used in crystal oscillator. All inputs are equipped with circuits against static discharge and transient excess voltage.

  • Page 47: Tsh22

    TSH22 13.4. 13.4.1. General Description The TSH22 is a dual bipolar operational amplifier offering a single supply operation from 3V to 30V with very good performances: medium speed (25MHz), unity gain stability and low noise. The TSH 22 is therefore an enhanced replacement of standard dual operational amplifiers. 13.4.2.

  • Page 48: Amic A43L2616

    AMIC A43L2616 13.6. 13.6.1. General Description The A43L2616-PH is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 X 1,048,576 words by 16 bits, fabricated with AMIC’s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle.
  • Page 49 27” TFT TV Service Manual 05/09/2005...

  • Page 50: Mx29Lv160T

    MX29LV160T 13.7. 13.7.1. General Description The MX29LV160T/B & MX29LV160AT/AB is a 16-megabit Flash memory organized as 2M bytes of 8 bits or 1M words of 16 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX29LV160T/B & MX29LV160AT/AB is packaged in 44-pin SOP, 48-pin TSOP and 48-ball CSP.

  • Page 51: 24C32

    24C32 13.8. 13.8.1. General Description The AT24C32/64 provides 32,768/65,536 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 4096/8192 words of 8 bits each. The device’s cascadable feature allows up to 8 devices to share a common 2-wire bus. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential.

  • Page 52: Stv0360

    STV0360 13.9. 13.9.1. General Description The STV0360 is a single-chip COFDM (coded orthogonal frequency division multiplex) demodulator that performs IF to MPEG-2 block processing of OFDM carriers. It is intended for digital terrestrial receivers for compressed video, sound and data services. The chip implements all the functions from the tuner IF output up to the MPEG-2 transport stream input.
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  • Page 55: Max809

    MAX809 13.10. 13.10.1. General Description The MAX803/MAX809/MAX810 are microprocessor (µP) supervisory circuits used to monitor the power supplies in µP and digital systems. They provide excellent circuit reliability and low cost by eliminating external components and adjustments when used with +5V, +3.3V,+3.0V, or +2.5V powered circuits. These circuits perform a single function: they assert a reset signal whenever the V supply voltage declines below a preset threshold, keeping it asserted for at least 140ms after V...

  • Page 56: Tdcc2345Tv39A

    TDCC2345TV39A 13.11. 13.11.1. General Description • Receiving System : Designed to cover all bands in VHF and UHF including digital terrestrial channels for DVB-T system. • Receiving Channel : 47 MHz ~ 862 MHz • Intermediate Frequency : Digital (center) 36.125 MHz •...
  • Page 57 13.12.2. Features • Module Interface • 2 independent module capability • Common Interface Standard compliant DVB_CI (CENELEC EN-50221) NRSS-B (SCTE IS-679 Part B) DAVIC v1.2 (CA0 interface) • Memory PCMCIA compliance (R2) 8-bit data access 26-bit address Memory Card • Attribute Memory access (CIS, Tupple) •...
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  • Page 61: Service Menu Settings

    14. SERVICE MENU SETTINGS All system, geometry and white balance alignments are performed in production service mode. Before starting the production mode alignments, make sure that all manual adjustments are done correctly. To start production mode alignments enter the MENU by pressing “MENU” button and then press the digits 4, 7, 2 and 5 respectively.
  • Page 62 scart prescale By pressing button, select scart prescaler. Press button to set the scart prescaler. Scart prescale can be adjusted between 0 and 127. nicam prescale By pressing button, select nicam prescaler. Press button to set the nicam prescaler. Nicam prescale can be adjusted between 0 and 127.

  • Page 63: Calibration Menu

    14.2. calibration menu By pressing “◄/►” buttons select the second icon. calibration menu appears on the screen. calibration initial APS burn-in mode color temp 5500K 7500K 9300K user 6500K 6500K auto video format down to change cal. settings, scrolling menu initial APS By pressing button, select initial APS.
  • Page 64 color space Displays the current color space used. RGB, YPbPr SMPTE240, YPbPr REC709 and YCbCr REC601. test pattern By pressing button, select test pattern. Press button to set the test pattern. The options are: none, solid color and vert bars. color components By pressing button, select color components.

  • Page 65: Deinterlacer Menu

    14.3. deinterlacer menu By pressing “◄/►” buttons select the third icon. deinterlacer menu appears on the screen. deinterlacer black expansion dcti dlti luminance peaking film mode film mode speed down for deinterlacer settings, scrolling menu black expansion By pressing button, select black expansion. Black expantion can be set to on or off by pressing button.
  • Page 66 film mode speed By pressing button, select film mode speed. Film mode speed can be set to 0, 1, 2 or 3 by pressing button. video on film. By pressing button, select vof. VOF can be set to on or off by pressing button.

  • Page 67: Factory Settings Menu

    14.4. factory settings menu By pressing “◄/►” buttons select the fourth icon. Factory settings menu appears on the screen. factory settings brightness contrast sharpness color volume hp volume down to change factory settings Brightness, contrast, sharpness, color, volume and headphone volume factory settings can be seen in this menu.

  • Page 68: Block Diagrams

    15. BLOCK DIAGRAMS SC1_AUDIO_L/R_IN Saw Filter SC2_AUDIO_L/R_IN DDC_DATA_PC 8 Ohms Sound IDTV_AUDIO_L/R_IN DDC_CLK_PC ST24LC21 TPA3002 QSS Main DDC_V (E2PROM) (Class D Amp) PC_VS Sound 8 Ohms TUNER MAIN_AUDIO_L/R 9886 (Main) IC113 MSP 34XX HP_L/R Headphone TDA1308 Saw Filter LINE_L/R_OUT HP_L/R DDC_DATA_DVI (Headphone Sound...
  • Page 69 BLOCK DIAGRAM - IDTV PART DIGITAL DIGITAL FRONTEND TUNER ST0360 FC_DATA(0-7) FC_CLK FC_SYNC FC_VALID +12V EMI DRAM 3.3V FROM 2.5V POWER (0-14) 1.8V SUPPLY CPU_ DATA CARD S+5V (0-7) INTERFACE Serial Interface RX,TX,IRQ S3.3V CONTROLLER STV0700 CMD(0-7) TO SDA 5550 CONTROLLER &...

  • Page 70: Circuit Diagrams

    16. CIRCUIT DIAGRAMS 27” TFT TV Service Manual 05/09/2005...
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