Sony STR-DB830 Service Manual page 33
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Also See for STR-DB830:
- Service manual (64 pages) ,
- Operating instructions manual (59 pages) ,
- Limited warranty (1 page)
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Pin No.
Pin Name
31
RIN–
32
RIN+
33
VREFL
34
VCOM
35
VREFH
36
A. 5V
37
A. GND
38
XTI
39
MCLKI
40
S/P
41
CS
42
CCLK
43
CDTI
44
CDTO
If pins TEST, ICKS0, ICKS1, PD, S/P, DFS, DEM0, DEM1, CAD0, CAD1, S/M, MCLK, SDOS are not driven, then TEST, ICKS0, ICKS1, CAD0, CAD1,
must be tied to either AVSS or AVDD. PD, S/P, DFS, DEM0, DEM1, S/M, MCLK, SDOS must be tied to either DVSS or DVDD.
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I/O
I
Rch analog negative input pin
I
Rch analog positive input pin
I
Negative voltage reference input pin, AVSS (Connected to ground)
Common voltage output pin, AVDD/2
O
Large external capacitor is used to reduce power-supply noise
I
Positive voltage reference input pin, AVDD
—
Analog power supply pin
—
Analog ground pin
I
X'tal input pin (Not used)
I
External master clock input pin if XTS = "L"
Parallel/serial select pin
I
"L": serial control mode, "H": parallel control mode (Connected to ground)
I
Chip select pin in serial mode
I
Control data clock pin in serial mode
I
Control data input in serial mode
O
Control data output pin in serial mode
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2 9
8
Description
Q Q
3
6 7
1 3
1 5
co
.
— 55 —
9 4
2 8
0 5
8
2 9
9 4
2 8
m
9 9
9 9
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